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KSZ8895MQ/RQ/FMQ
Integrated 5-Port 10/100 Managed Ethernet Switch with MII/RMII interface
Rev. 1.2
General Description
The KSZ8895MQ/RQ/FMQ is a highly-integrated Layer 2 managed five-port switch with optimized design and plentiful features. It is designed for cost-sensitive 10/100Mbps five-port switch systems with lowest power consumption, on-chip termination and internal core power controller. These features will save more system cost. It supports high-performance memory bandwidth, shared memory based switch fabric with non-blocking configuration. It also provides an extensive feature set such as power management, programmable rate limit and priority ratio, tag/port-based VLAN, packets filtering, four queues QoS prioritization, management interfaces and MIB counters. KSZ8895 family provides multiple CPU data interfaces to effectively address both current and emerging fast Ethernet applications when port 5 is configured to separate MAC5 with SW5-MII/RMII and PHY5 with P5-MII/RMII interfaces.
The configurations provided by the KSZ8895 family enables the flexibility to meet different requirements: * * * KSZ8895MQ: Five 10/100Base-T/TX transceivers, one SW5-MII and one P5-MII interface KSZ8895RQ: Five 10/100Base-T/TX transceivers, one SW5-RMII and one P5-RMII interface KSZ8895FMQ: Three 10/100Base-T/TX transceiver on Ports 1, 2, 5 and two 100Base-FX transceivers on Ports 3, 4, one SW5-MII and one P5-MII interface
All registers of MACs and PHYs units can be managed by the SPI or the SMI interface. MIIM registers can be accessed through the MDC/MDIO interface. EEPROM can set all control registers for the unmanaged mode.
Functional Diagram
Note: SW5 indicates the MAC5 of the switch side, P5 indicates the PHY5 of the Port 5.
Micrel Inc. * 2180 Fortune Drive * San Jose, CA 95131 * USA * tel +1 (408) 944-0800 * fax + 1 (408) 474-1000 * http://www.micrel.com
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* Non-blocking switch fabric assures fast packet delivery by utilizing an 1K MAC address lookup table and a store-and-forward architecture. On-chip 64Kbyte memory for frame buffering (not shared with 1K unicast address table). Full duplex IEEE 802.3x flow control (PAUSE) with force mode option. Half-duplex back pressure flow control. HP Auto MDI/MDI-X and IEEE Auto crossover support. SW-MII interface supports both MAC mode and PHY mode. 7-wire serial network interface (SNI) support for legacy MAC. Per port LED Indicators for link, activity, and 10/100 speed. Register port status support for link, activity, full/half duplex and 10/100 speed. On-chip terminations and internal biasing technology for cost down and lowest power consumption.
Features
Advanced Switch Features * IEEE 802.1q VLAN support for up to 128 VLAN groups (full-range 4096 of VLAN IDs). * Static MAC table supports up to 32 entries. * VLAN ID tag/untag options, per port basis * IEEE 802.1p/q tag insertion or removal on a per port basis based on ingress port (egress). * Programmable rate limiting at the ingress and egress on a per port basis. * Jitter-free per packet based rate limiting support. * Broadcast storm protection with percentage control (global and per port basis). * IEEE 802.1d rapid spanning tree protocol RSTP support. * Tail tag mode (1 byte added before FCS) support at Port 5 to inform the processor which ingress port receives the packet. * 2.8Gbps high-performance memory bandwidth and shared memory based switch fabric with fully nonblocking configuration. * Dual MII with MAC5 and PHY5 on port 5, SW5MII/RMII for MAC 5 and P5-MII/RMII for PHY 5. * Enable/Disable option for huge frame size up to 2000 Bytes per frame. * IGMP v1/v2 snooping (Ipv4) support for multicast packet filtering. * IPv4/IPv6 QoS support. * Support unknown unicast/multicast address and unknown VID packet filtering. * Self-address filtering. Comprehensive Configuration Register Access * Serial management interface (MDC/MDIO) to all PHYs registers and SMI interface (MDC/MDIO) to all registers. * High speed SPI (up to 25MHz) and I2C master Interface to all internal registers. * I/0 pins strapping and EEPROM to program selective registers in unmanaged switch mode. *
Control registers configurable on the fly (port-priority, 802.1p/d/q, AN).
* * * * * * * *
*
Switch Monitoring Features * Port mirroring/monitoring/sniffing: ingress and/or egress traffic to any port or MII. * MIB counters for fully compliant statistics gathering 34 MIB counters per port. * Loop-back support for MAC, PHY and remote diagnostic of failure. * Interrupt for the link change on any ports. Low Power Dissipation * Full-chip hardware power-down. * Full-chip software power-down and per port software power down. * Energy-detect mode support < 100mW full chip-power consumption when all ports have no activity. * Very-low full chip power consumption (<0.5W), without extra power consumption on transformers. * Dynamic clock tree shutdown feature. * Voltages: Single 3.3V supply with 3.3V VDDIO and Internal 1.2V LDO controller enabled, or external 1.2V LDO solution. - Analog VDDAT 3.3V only. - VDDIO support 3.3V, 2.5V and 1.8V. - Low 1.2V core power . * 0.13um CMOS technology. * Commercial temperature range: 0C to +70C. * Industrial Temperature Range: -40oC to +85oC. * Available in 128-pin PQFP, lead-free package.
QoS/CoS Packet Prioritization Support * Per port, 802.1p and DiffServ-based. * 1/2/4-queue QoS prioritization selection. * Programmable weighted fair queuing for ratio control. * Re-mapping of 802.1p priority field per port basis. Integrated Five-Port 10/100 Ethernet Switch * New generation switch with five MACs and five PHYs with fully compliant with IEEE 802.3u standard. * PHYs designed with patented enhanced mixed-signal technology. January 2011 2
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KSZ8895MQ/RQ/FMQ - - - - - - IPTV POF SOHO Residential Gateway Broadband Gateway/Firewall/VPN Integrated DSL/Cable Modem Wireless LAN access point + gateway Standalone 10/100 switch
Applications
- - - - - Typical VoIP Phone Set-top/Game Box Automotive Industrial Control
Ordering Information
Part Number KSZ8895MQ KSZ8895MQI KSZ8895RQ KSZ8895RQI
(1) (1) (1) (1) (1)
Junction Temperature Range 0C to 70C -40C to +85C 0C to 70C -40C to +85C 0C to 70C
Package 128-Pin LQFP 128-Pin LQFP 128-Pin LQFP 128-Pin LQFP 128-Pin LQFP 128-Pin LQFP
Lead Finish/Grade Pb-Free/Commercial Pb-Free/Industrial Pb-Free/Commercial Pb-Free/Industrial Pb-Free/Commercial Pb-Free/Industrial
KSZ8895FMQ
KSZ8895FMQI -40C to +85C Note: 1. Please consult sales for the availability
Revision History
Revision 1.0 1.1 1.2 Date 09/13/10 11/16/10 01/20/11 Description Initial document created Remove TMQ part Update the ordering information and some data.
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Contents
Pin Configuration ..........................................................................................................................................................13 Pin Configuration ..........................................................................................................................................................13 Pin Description ..............................................................................................................................................................14 Pin for Strap-in Options................................................................................................................................................22 Introduction ...................................................................................................................................................................25 Functional Overview: Physical Layer Transceiver ....................................................................................................25 100BASE-TX Transmit ...............................................................................................................................................25 100BASE-TX Receive ................................................................................................................................................25 PLL Clock Synthesizer................................................................................................................................................26 Scrambler/De-Scrambler (100BASE-TX only)............................................................................................................26 100BASE-FX Operation..............................................................................................................................................26 100BASE-FX Signal Detection ...................................................................................................................................26 100BASE-FX far End fault ..........................................................................................................................................26 10BASE-T Transmit....................................................................................................................................................26 10BASE-T Receive .....................................................................................................................................................26 MDI/MDI-X Auto Crossover ........................................................................................................................................26 Straight Cable .........................................................................................................................................................27 Crossover Cable .....................................................................................................................................................28 Auto-Negotiation .........................................................................................................................................................28 On-chip Termination Resistors ...................................................................................................................................30 Internal 1.2V LDO Controller ......................................................................................................................................30 Functional Overview: Power Management .................................................................................................................30 Normal Operation Mode .............................................................................................................................................30 Energy Detect Mode ...................................................................................................................................................31 Soft Power Down Mode ..............................................................................................................................................31 Power Saving Mode....................................................................................................................................................31 Port based Power Down Mode ...................................................................................................................................31 Functional Overview: Switch Core ..............................................................................................................................31 Address Look-Up ........................................................................................................................................................31 Learning ......................................................................................................................................................................31 Migration .....................................................................................................................................................................32 Aging ...........................................................................................................................................................................32 Forwarding ..................................................................................................................................................................32 Switching Engine ........................................................................................................................................................32 Media Access Controller (MAC) Operation ................................................................................................................32 Inter-Packet Gap (IPG) ...........................................................................................................................................32 Backoff Algorithm....................................................................................................................................................32 Late Collision ..........................................................................................................................................................32 Illegal Frames .........................................................................................................................................................32 Flow Control............................................................................................................................................................33 Half-Duplex Back Pressure ....................................................................................................................................36 Broadcast Storm Protection....................................................................................................................................36 MII Interface Operation ...............................................................................................................................................37 January 2011 4
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Port 5 PHY 5 P5-MII/RMII Interface............................................................................................................................37 Port 5 MAC 5 SW5-MII Interface for the KSZ8895MQ/FMQ ......................................................................................38 Port 5 MAC 5 Switch SW5-RMII Interface for the KSZ8895RQ .................................................................................39 SNI Interface Operation ..............................................................................................................................................41 Advanced Functionality................................................................................................................................................42 QoS Priority Support ...................................................................................................................................................42 Port-Based Priority..................................................................................................................................................42 802.1p-Based Priority .............................................................................................................................................42 DiffServ-Based Priority ...........................................................................................................................................43 Spanning Tree Support...............................................................................................................................................43 Rapid Spanning Tree Support ....................................................................................................................................44 Tail Tagging Mode ......................................................................................................................................................45 IGMP Support .............................................................................................................................................................46 Port Mirroring Support ................................................................................................................................................46 VLAN Support .............................................................................................................................................................46 Rate Limiting Support .................................................................................................................................................47 Ingress Rate Limit...................................................................................................................................................47 Egress Rate Limit ...................................................................................................................................................48 Transmit Queue Ratio Programming......................................................................................................................48 Filtering for Self-Address, Unknown Unicast/Multicast Address and Unknown VID Packet/IP Multicast ..................48 Configuration Interface ...............................................................................................................................................48 2 I C Master Serial Bus Configuration .......................................................................................................................48 SPI Slave Serial Bus Configuration ........................................................................................................................49 MII Management Interface (MIIM) ..........................................................................................................................52 Serial Management Interface (SMI)........................................................................................................................52 Register Description .....................................................................................................................................................54 Global Registers .........................................................................................................................................................56 Register 0 (0x00): Chip ID0 ....................................................................................................................................56 Register 1 (0x01): Chip ID1 / Start Switch..............................................................................................................56 Register 2 (0x02): Global Control 0 ........................................................................................................................56 Register 3 (0x03): Global Control 1 ........................................................................................................................57 Register 4 (0x04): Global Control 2 ........................................................................................................................58 Register 5 (0x05): Global Control 3 ........................................................................................................................59 Register 6 (0x07): Global Control 4 ........................................................................................................................60 Register 7 (0x07): Global Control 5 ........................................................................................................................60 Register 8 (0x08): Global Control 6 ........................................................................................................................60 Register 9 (0x09): Global Control 7 ........................................................................................................................61 Register 10 (0x0A): Global Control 8......................................................................................................................62 Register 11 (0x0B): Global Control 9......................................................................................................................62 Register 12 (0x0C): Global Control 10 ...................................................................................................................63 Register 13 (0x0D): Global Control 11 ...................................................................................................................63 Register 14 (0x0E): Power Down Management Control 1 .....................................................................................63 Register 15 (0x0F): Power Down Management Control 2....................................... Error! Bookmark not defined. Port Registers .............................................................................................................................................................65 January 2011 5
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Register 16 (0x10): Port 1 Control 0.......................................................................................................................65 Register 32 (0x20): Port 2 Control 0.......................................................................................................................65 Register 48 (0x30): Port 3 Control 0.......................................................................................................................65 Register 64 (0x40): Port 4 Control 0.......................................................................................................................65 Register 80 (0x50): Port 5 Control 0.......................................................................................................................65 Register 17 (0x11): Port 1 Control 1.......................................................................................................................66 Register 33 (0x21): Port 2 Control 1.......................................................................................................................66 Register 49 (0x31): Port 3 Control 1.......................................................................................................................66 Register 65 (0x41): Port 4 Control 1.......................................................................................................................66 Register 81 (0x51): Port 5 Control 1.......................................................................................................................66 Register 18 (0x12): Port 1 Control 2.......................................................................................................................67 Register 34 (0x22): Port 2 Control 2.......................................................................................................................67 Register 50 (0x32): Port 3 Control 2.......................................................................................................................67 Register 66 (0x42): Port 4 Control 2.......................................................................................................................67 Register 82 (0x52): Port 5 Control 2.......................................................................................................................67 Register 19 (0x13): Port 1 Control 3.......................................................................................................................68 Register 35 (0x23): Port 2 Control 3.......................................................................................................................68 Register 51 (0x33): Port 3 Control 3.......................................................................................................................68 Register 67 (0x43): Port 4 Control 3.......................................................................................................................68 Register 83 (0x53): Port 5 Control 3.......................................................................................................................68 Register 20 (0x14): Port 1 Control 4.......................................................................................................................68 Register 36 (0x24): Port 2 Control 4.......................................................................................................................68 Register 52 (0x34): Port 3 Control 4.......................................................................................................................68 Register 68 (0x44): Port 4 Control 4.......................................................................................................................68 Register 84 (0x54): Port 5 Control 4.......................................................................................................................68 Register 87 (0x57): RMII Management Control Register .......................................................................................68 Register 25 (0x19): Port 1 Status 0 ........................................................................................................................69 Register 41 (0x29): Port 2 Status 0 ........................................................................................................................69 Register 57 (0x39): Port 3 Status 0 ........................................................................................................................69 Register 73 (0x49): Port 4 Status 0 ........................................................................................................................69 Register 89 (0x59): Port 5 Status 0 ........................................................................................................................69 Register 26 (0x1A): Port 1 PHY Special Control/Status.........................................................................................69 Register 42 (0x2A): Port 2 PHY Special Control/Status.........................................................................................69 Register 58 (0x3A): Port 3 PHY Special Control/Status.........................................................................................69 Register 74 (0x4A): Port 4 PHY Special Control/Status.........................................................................................69 Register 90 (0x5A): Port 5 PHY Special Control/Status.........................................................................................69 Register 27 (0x1B): Reserved ................................................................................................................................70 Register 43 (0x2B): Reserved ................................................................................................................................70 Register 59 (0x3B): Reserved ................................................................................................................................70 Register 75 (0x4B): Reserved ................................................................................................................................70 Register 91 (0x5B): Reserved ................................................................................................................................70 Register 28 (0x1C): Port 1 Control 12 ....................................................................................................................70 Register 44 (0x2C): Port 2 Control 12 ....................................................................................................................70 Register 60 (0x3C): Port 3 Control 12 ....................................................................................................................70 January 2011 6
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Register 76 (0x4C): Port 4 Control 12 ....................................................................................................................70 Register 92 (0x5C): Port 5 Control 12 ....................................................................................................................70 Register 29 (0x1D): Port 1 Control 13 ....................................................................................................................71 Register 45 (0x2D): Port 2 Control 13 ....................................................................................................................71 Register 61 (0x3D): Port 3 Control 13 ....................................................................................................................71 Register 77 (0x4D): Port 4 Control 13 ....................................................................................................................71 Register 93 (0x5D): Port 5 Control 13 ....................................................................................................................71 Register 30 (0x1E): Port 1 Status 1........................................................................................................................72 Register 46 (0x2E): Port 2 Status 1........................................................................................................................72 Register 62 (0x3E): Port 3 Status 1........................................................................................................................72 Register 78 (0x4E): Port 4 Status 1........................................................................................................................72 Register 94 (0x5E): Port 5 Status 1........................................................................................................................72 Register 31 (0x1F): Port 1 Control 14 and Status 2 ...............................................................................................72 Register 47 (0x2F): Port 2 Control 14 and Status 2 ...............................................................................................72 Register 63 (0x3F): Port 3 Control 14 and Status 2 ...............................................................................................72 Register 79 (0x4F): Port 4 Control 14 and Status 2 ...............................................................................................72 Register 95 (0x5F): Port 5 Control 14 and Status 2 ...............................................................................................72 Advanced Control Registers .......................................................................................................................................73 Register 104 (0x68): MAC Address Register 0 ......................................................................................................73 Register 105 (0x69): MAC Address Register 1 ......................................................................................................73 Register 106 (0x6A): MAC Address Register 2......................................................................................................73 Register 107 (0x6B): MAC Address Register 3......................................................................................................73 Register 108 (0x6C): MAC Address Register 4......................................................................................................73 Register 109 (0X6D): MAC Address Register 5 .....................................................................................................73 Register 110 (0x6E): Indirect Access Control 0 .....................................................................................................73 Register 111 (0x6F): Indirect Access Control 1......................................................................................................74 Register 112 (0x70): Indirect Data Register 8 ........................................................................................................74 Register 113 (0x71): Indirect Data Register 7 ........................................................................................................74 Register 114 (0x72): Indirect Data Register 6 ........................................................................................................74 Register 115 (0x73): Indirect Data Register 5 ........................................................................................................74 Register 116 (0x74): Indirect Data Register 4 ........................................................................................................74 Register 117 (0x75): Indirect Data Register 3 ........................................................................................................74 Register 118 (0x76): Indirect Data Register 2 ........................................................................................................74 Register 119 (0x77): Indirect Data Register 1 ........................................................................................................74 Register 120 (0x78): Indirect Data Register 0 ........................................................................................................74 Register 124 (0x7C): Interrupt Status Register ......................................................................................................75 Register 125 (0x7D): Interrupt Mask Register ........................................................................................................75 Register 128 (0x80): Global Control 12 ..................................................................................................................76 Register 129 (0x81): Global Control 13 ..................................................................................................................76 Register 130 (0x82): Global Control 14 ..................................................................................................................76 Register 131 (0x83): Global Control 15 ..................................................................................................................77 Register 132 (0x84): Global Control 16 ..................................................................................................................77 Register 133(0x85): Global Control 17 ...................................................................................................................77 Register 134 (0x86): Global Control 18 ..................................................................................................................77 January 2011 7
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Register 135 (0x87): Global Control 19 ..................................................................................................................78 Register 144 (0x90): TOS Priority Control Register 0 ............................................................................................78 Register 145 (0x91): TOS Priority Control Register 1 ............................................................................................78 Register 146 (0x92): TOS Priority Control Register 2 ............................................................................................79 Register 147 (0x93): TOS Priority Control Register 3 ............................................................................................79 Register 148 (0x94): TOS Priority Control Register 4 ............................................................................................79 Register 149 (0x95): TOS Priority Control Register 5 ............................................................................................79 Register 150 (0x96): TOS Priority Control Register 6 ............................................................................................79 Register 151 (0x97): TOS Priority Control Register 7 ............................................................................................79 Register 152 (0x98): TOS Priority Control Register 8 ............................................................................................79 Register 153 (0x99): TOS Priority Control Register 9 ............................................................................................80 Register 154 (0x9A): TOS Priority Control Register 10..........................................................................................80 Register 155 (0x9B): TOS Priority Control Register 11..........................................................................................80 Register 156 (0x9C): TOS Priority Control Register 12..........................................................................................80 Register 157 (0x9D): TOS Priority Control Register 13..........................................................................................80 Register 158 (0x9E): TOS Priority Control Register 14..........................................................................................80 Register 159 (0x9F): TOS Priority Control Register 15 ..........................................................................................80 Register 176 (0xB0): Port 1 Control 8 ....................................................................................................................81 Register 192 (0xC0): Port 2 Control 8 ....................................................................................................................81 Register 208 (0xD0): Port 3 Control 8 ....................................................................................................................81 Register 224 (0xE0): Port 4 Control 8 ....................................................................................................................81 Register 240 (0xF0): Port 5 Control 8.....................................................................................................................81 Register 177 (0xB1): Port 1 Control 9 ....................................................................................................................82 Register 193 (0xC1): Port 2 Control 9 ....................................................................................................................82 Register 209 (0xD1): Port 3 Control 9 ....................................................................................................................82 Register 225 (0xE1): Port 4 Control 9 ....................................................................................................................82 Register 241 (0xF1): Port 5 Control 9.....................................................................................................................82 Register 178 (0xB2): Port 1 Control 10 ..................................................................................................................82 Register 194 (0xC2): Port 2 Control 10 ..................................................................................................................82 Register 210 (0xD2): Port 3 Control 10 ..................................................................................................................82 Register 226 (0xE2): Port 4 Control 10 ..................................................................................................................82 Register 242 (0xF2): Port 5 Control 10...................................................................................................................82 Register 179 (0xB3): Port 1 Control 11 ..................................................................................................................82 Register 195 (0xC3): Port 2 Control 11 ..................................................................................................................82 Register 211 (0xD3): Port 3 Control 11 ..................................................................................................................82 Register 227 (0xE3): Port 4 Control 11 ..................................................................................................................82 Register 243 (0xF3): Port 5 Control 11...................................................................................................................82 Register 180 (0xB4): Port 1 Control 12 ..................................................................................................................83 Register 196 (0xC4): Port 2 Control 12 ..................................................................................................................83 Register 212 (0xD4): Port 3 Control 12 ..................................................................................................................83 Register 228 (0xE4): Port 4 Control 12 ..................................................................................................................83 Register 244 (0xF4): Port 5 Control 12...................................................................................................................83 Register 181 (0xB5): Port 1 Control 13 ..................................................................................................................83 Register 197 (0xC5): Port 2 Control 13 ..................................................................................................................83 January 2011 8
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Register 213 (0xD5): Port 3 Control 13 ..................................................................................................................83 Register 229 (0xE5): Port 4 Control 13 ..................................................................................................................83 Register 245 (0xF5): Port 5 Control 13...................................................................................................................83 Register 182 (0xB6): Port 1 Rate Limit Control ......................................................................................................83 Register 198 (0xC6): Port 2 Rate Limit Control ......................................................................................................83 Register 214 (0xD6): Port 3 Rate Limit Control ......................................................................................................83 Register 230 (0xE6): Port 4 Rate Limit Control ......................................................................................................83 Register 246 (0xF6): Port 5 Rate Limit Control ......................................................................................................83 Register 183 (0xB7): Port 1 Priority 0 Ingress Limit Control 1................................................................................84 Register 199 (0xC7): Port 2 Priority 0 Ingress Limit Control 1 ...............................................................................84 Register 215 (0xD7): Port 3 Priority 0 Ingress Limit Control 1 ...............................................................................84 Register 231 (0xE7): Port 4 Priority 0 Ingress Limit Control 1................................................................................84 Register 247 (0xF7): Port 5 Priority 0 Ingress Limit Control 1................................................................................84 Register 184 (0xB8): Port 1 Priority 1 Ingress Limit Control 2................................................................................84 Register 200 (0xC8): Port 2 Priority 1 Ingress Limit Control 2 ...............................................................................84 Register 216 (0xD8): Port 3 Priority 1 Ingress Limit Control 2 ...............................................................................84 Register 232 (0xE8): Port 4 Priority 1 Ingress Limit Control 2................................................................................84 Register 248 (0xF8): Port 5 Priority 1 Ingress Limit Control 2................................................................................84 Register 185 (0xB9): Port 1 Priority 2 Ingress Limit Control 3................................................................................84 Register 201 (0xC9): Port 2 Priority 2 Ingress Limit Control 3 ...............................................................................84 Register 217 (0xD9): Port 3 Priority 2 Ingress Limit Control 3 ...............................................................................84 Register 233 (0xE9): Port 4 Priority 2 Ingress Limit Control 3................................................................................84 Register 249 (0xF9): Port 5 Priority 2 Ingress Limit Control 3................................................................................84 Register 186 (0xBA): Port 1 Priority 3 Ingress Limit Control 4 ...............................................................................84 Register 202 (0xCA): Port 2 Priority 3 Ingress Limit Control 4 ...............................................................................84 Register 218 (0xDA): Port 3 Priority 3 Ingress Limit Control 4 ...............................................................................84 Register 234 (0xEA): Port 4 Priority 3 Ingress Limit Control 4 ...............................................................................84 Register 250 (0xFA): Port 5 Priority 3 Ingress Limit Control 4 ...............................................................................84 Register 187 (0xBB): Port 1 Queue 0 Egress Limit Control 1 ................................................................................85 Register 203 (0xCB): Port 2 Queue 0 Egress Limit Control 1 ................................................................................85 Register 219 (0xDB): Port 3 Queue 0 Egress Limit Control 1 ................................................................................85 Register 235 (0xEB): Port 4 Queue 0 Egress Limit Control 1 ................................................................................85 Register 251 (0xFB): Port 5 Queue 0 Egress Limit Control 1 ................................................................................85 Register 188 (0xBC) : Port 1 Queue 1 Egress Limit Control 2 ...............................................................................85 Register 204 (0xCC) : Port 2 Queue 1 Egress Limit Control 2...............................................................................85 Register 220 (0xDC) : Port 3 Queue 1 Egress Limit Control 2...............................................................................85 Register 236 (0xEC) : Port 4 Queue 1 Egress Limit Control 2 ...............................................................................85 Register 252 (0xFC) : Port 5 Queue 1 Egress Limit Control 2 ...............................................................................85 Register 189 (0xBD): Port 1 Queue 2 Egress Limit Control 3 ................................................................................85 Register 205 (0xCD): Port 2 Queue 2 Egress Limit Control 3................................................................................85 Register 221 (0xDD): Port 3 Queue 2 Egress Limit Control 3................................................................................85 Register 237 (0xED): Port 4 Queue 2 Egress Limit Control 3 ................................................................................85 Register 253 (0xFD): Port 5 Queue 2 Egress Limit Control 3 ................................................................................85 Register 190 (0xBE) : Port 1 Queue 3 Egress Limit Control 4 ...............................................................................85 January 2011 9
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Register 206 (0xCE) : Port 2 Queue 3 Egress Limit Control 4 ...............................................................................85 Register 222 (0xDE) : Port 3 Queue 3 Egress Limit Control 4 ...............................................................................85 Register 238 (0xEE): Port 4 Queue 3 Egress Limit Control 4 ................................................................................85 Register 254 (0xFE): Port 5 Queue 3 Egress Limit Control 4 ................................................................................85 Data Rate Selection Table in 100BT ..........................................................................................................................87 Data Rate Selection Table in 10BT ............................................................................................................................87 Register 191(0xBF): Testing Register ....................................................................................................................88 Register 207(0xCF): Reserved Control Register...................................................................................................88 Register 223(0xDF): Test Register 2......................................................................................................................88 Register 239(0xEF): Test Register 3 ......................................................................................................................88 Register 255(0xFF): Testing Register4 ..................................................................................................................88 Static MAC Address Table ...........................................................................................................................................89 VLAN Table ....................................................................................................................................................................91 Dynamic MAC Address Table ......................................................................................................................................93 MIB (Management Information Base) Counters .........................................................................................................94 MIIM Registers ...............................................................................................................................................................97 Register 0h: MII Control ..............................................................................................................................................97 Register 1h: MII Status ...............................................................................................................................................97 Register 2h: PHYID HIGH ..........................................................................................................................................98 Register 3h: PHYID LOW ...........................................................................................................................................98 Register 4h: Advertisement Ability..............................................................................................................................98 Register 5h: Link Partner Ability .................................................................................................................................98 Register 1dh: LinkMD Control/Status ........................................................................................................................99 Register 1fh: PHY Special Control/Status ..................................................................................................................99 (1) Absolute Maximum Ratings ....................................................................................................................................100 (2) Operating Ratings ....................................................................................................................................................100 (4, 5) Electrical Characteristics ......................................................................................................................................100 Timing Diagrams .........................................................................................................................................................102 EEPROM Timing.......................................................................................................................................................102 SNI Timing ................................................................................................................................................................103 MII Timing .................................................................................................................................................................104 RMII Timing...............................................................................................................................................................106 SPI Timing ................................................................................................................................................................107 Auto-Negotiation Timing ...........................................................................................................................................109 MDC/MDIO Timing....................................................................................................................................................110 Reset Timing.............................................................................................................................................................111 Reset Circuit Diagram...............................................................................................................................................112 (1) Selection of Isolation Transformer .........................................................................................................................113 Selection of Reference Crystal ..................................................................................................................................113 Package Information ...................................................................................................................................................114
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List of Figures
Figure 1. Typical Straight Cable Connection ............................................................................................................... 27 Figure 2. Typical Crossover Cable Connection ........................................................................................................... 28 Figure 3. Auto-Negotiation ........................................................................................................................................... 29 Figure 4. Destination Address Lookup Flow Chart, Stage 1 ........................................................................................ 34 Figure 5. Destination Address Resolution Flow Chart, Stage 2................................................................................... 35 Figure 6. 802.1p Priority Field Format.......................................................................................................................... 42 Figure 7. Tail Tag Frame Format .................................................................................................................................. 45 Figure 8. KSZ8895MQ/RQ/FMQ EEPROM Configuration Timing Diagram ................................................................ 49 Figure 9. SPI Write Data Cycle .................................................................................................................................... 50 Figure 10. SPI Read Data Cycle .................................................................................................................................. 50 Figure 11. SPI Multiple Write ....................................................................................................................................... 51 Figure 12. SPI Multiple Read ....................................................................................................................................... 51 Figure 13. EEPROM Interface Input Receive Timing Diagram.................................................................................. 102 Figure 14. EEPROM Interface Output Transmit Timing Diagram .............................................................................. 102 Figure 15. SNI Input Timing ....................................................................................................................................... 103 Figure 16. SNI Output Timing .................................................................................................................................... 103 Figure 17. MAC Mode MII Timing - Data Received from MII .................................................................................... 104 Figure 18. MAC Mode MII Timing - Data Transmitted from MII ................................................................................ 104 Figure 19. PHY Mode MII Timing - Data Received from MII..................................................................................... 105 Figure 20. PHY Mode MII Timing - Data Transmitted from MII................................................................................. 105 Figure 21. RMII Timing - Data Received from RMII .................................................................................................. 106 Figure 22. RMII Timing - Data Transmitted to RMII .................................................................................................. 106 Figure 23. SPI Input Timing ....................................................................................................................................... 107 Figure 24. SPI Output Timing..................................................................................................................................... 108 Figure 25: Auto-Negotiation Timing ........................................................................................................................... 109 Figure 26. MDC/MDIO Timing.................................................................................................................................... 110 Figure 27. Reset Timing ............................................................................................................................................. 111 Figure 28. Recommended Reset Circuit .................................................................................................................... 112 Figure 29. Recommended Circuit for Interfacing with CPU/FPGA Reset.................................................................. 112
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List of Tables
Table 1. MDI/MDI-X Pin Definitions ............................................................................................................................. 27 Table 2. Internal Function Block Status ........................................................................................................................ 30 Table 3. Port 5 PHY P5-MII/RMII Signals .................................................................................................................... 37 Table 4. Switch MAC5 MII Signals............................................................................................................................... 38 Table 5. Port 5 MAC5 SW5-RMII Connection.............................................................................................................. 40 Table 6. SNI Signals..................................................................................................................................................... 41 Table 7. Tail Tag Rules ................................................................................................................................................ 45 Table 8. FID+DA Look-Up in the VLAN Mode ............................................................................................................. 47 Table 9. FID+SA Look-Up in the VLAN Mode.............................................................................................................. 47 Table 10. SPI Connections .......................................................................................................................................... 50 Table 11. MII Management Interface Frame Format ................................................................................................... 52 Table 12. Serial Management Interface (SMI) Frame Format ..................................................................................... 52 Table 13. 100BT Rate Selection for the Rate limit....................................................................................................... 87 Table 14. 10BT Rate Selection for the Rate Limit........................................................................................................ 87 Table 15. Static MAC Address Table ........................................................................................................................... 89 Table 16. VLAN Table .................................................................................................................................................. 91 Table 17. VLAN ID and Indirect Registers ................................................................................................................... 92 Table 18. Dynamic MAC Address Table ...................................................................................................................... 93 Table 19. Port1 MIB Counter Indirect Memory Offerts................................................................................................. 94 Table 20. Format of "Per Port" MIB Counter ................................................................................................................ 95 Table 21. All Port Dropped Packet MIB Counters........................................................................................................ 95 Table 22. Format of "All Dropped Packet" MIB Counter .............................................................................................. 95 Table 23. EEPROM Timing Parameters .................................................................................................................... 102 Table 24. SNI Timing Parameters.............................................................................................................................. 103 Table 25. MAC Mode MII Timing Parameters............................................................................................................ 104 Table 26. PHY Mode MII Timing Parameters ............................................................................................................ 105 Table 27. RMII Timing Parameters ............................................................................................................................ 106 Table 28. SPI Input Timing Parameters ..................................................................................................................... 107 Table 29. SPI Output Timing Parameters .................................................................................................................. 108 Table 30. Auto-Negotiation Timing Parameters ......................................................................................................... 109 Table 31. MDC/MDIO Typical Timing Parameters..................................................................................................... 110 Table 32. Reset Timing Parameters .......................................................................................................................... 111 Table 33. Transformer Selection Criteria ................................................................................................................... 113 Table 34. Qualified Magnetic Vendors ....................................................................................................................... 113 Table 35. Typical Reference Crystal Characteristics ................................................................................................. 113
January 2011
12
M9999-012011-1.2
Micrel, Inc.
January 2011
Pin Configuration
128-Pin PQFP
13
MDIXDIS GNDA VDDAR RXP1 RXM1 GNDA TXP1 TXM1 VDDAT RXP2 RXM2 GNDA TXP2 TXM2 VDDAR GNDA ISET VDDAT RXP3 RXM3 GNDA TXP3 TXM3 VDDAT RXP4 RXM4 GNDA TXP4 TXM4 GNDA VDDAR RXP5 RXM5 GNDA TXP5 TXM5 VDDAT FXSD3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
LED2-1 LED2-2 VDDIO GNDD LED3-0 LED3-1 LED3-2 LED4-0 LED4-1 LED4-2 LED5-0 LED5-1 LED5-2 VDDC GNDD SCONF0 SCONF1 SCRS SCOL SMRXD0 SMRXD1 SMRXD2 SMRXD3 SMRXDV/SMCRSDV SMRXC VDDIO GNDD SMTXC/SMREFCLK SMTXER SMTXD0 SMTXD1 SMTXD2 SMTXD3 SMTXEN PCOL PCRS PMRXER PMRXD0
KSZ8895MQ/RQ/FMQ
M9999-012011-1.2
Micrel, Inc.
KSZ8895MQ/RQ/FMQ
Pin Description
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Pin Name MDI-XDIS GNDA VDDAR RXP1 RXM1 GNDA TXP1 TXM1 VDDAT RXP2 RXM2 GNDA TXP2 TXM2 VDDAR GNDA ISET VDDAT RXP3 RXM3 GNDA TXP3 TXM3 VDDAT RXP4 RXM4 GNDA TXP4 TXM4 GNDA VDDAR RXP5 RXM5 GNDA TXP5 TXM5 P I I GND O O P I I GND O O GND P I I GND O O 5 5 5 5 4 4 4 4 3 3 3 3 Type
(1)
Port 1-5
Pin Function
(2)
LPD GND P I I GND O O P I I GND O O P GND
Disable auto MDI/MDI-X. PD (default) = normal operation. PU = disable auto MDI/MDI-X on all ports. Analog ground. 1.2V analog VDD. Physical receive signal + (differential). Physical receive signal - (differential). Analog ground. Physical transmit signal + (differential). Physical transmit signal - (differential). 3.3V analog VDD. Physical receive signal + (differential). Physical receive signal - (differential). Analog ground. Physical transmit signal + (differential). Physical transmit signal - (differential). 1.2V analog VDD. Analog ground. Set physical transmit output current. Pull-down with a 12.4k1% resistor. 3.3V analog VDD. Physical receive signal + (differential). Physical receive signal - (differential). Analog ground. Physical transmit signal + (differential). Physical transmit signal - (differential). 3.3V analog VDD. Physical receive signal + (differential). Physical receive signal - (differential). Analog ground. Physical transmit signal + (differential). Physical transmit signal - (differential). Analog ground. 1.2V analog VDD. Physical receive signal + (differential). Physical receive signal - (differential). Analog ground. Physical transmit signal + (differential). Physical transmit signal - (differential).
1 1 1 1 2 2 2 2
January 2011
14
M9999-012011-1.2
Micrel, Inc.
KSZ8895MQ/RQ/FMQ
Pin Number 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
Pin Name VDDAT FXSD3 FXSD4 NC NC NC NC NC NC NC PWRDN_N INTR_N GNDD VDDC PMTXEN PMTXD3 PMTXD2 PMTXD1 PMTXD0 PMTXER PMTXC/PMREFCLK GNDD VDDIO PMRXC
Type P
(1)
Port
Pin Function
(2)
IPD IPD NC NC NC NC NC NC NC IPU OPU GND P IPD IPD IPD IPD IPD IPD I/O GND P I/O
3 4
3.3V analog VDD. FMQ: Fiber signal detect pin for Port 3. MQ/RQ: no connection. FMQ: Fiber signal detect pin for Port 4. MQ/RQ: no connection. No connect. No connect. No connect. No connect. No connect. No connect. No connect. Full-chip power down. Active low. Interrupt. This pin is Open-Drain output pin. Digital ground. 1.2V digital core VDD.
5 5 5 5 5 5 5
PHY[5] MII/RMII transmit enable. MQ/FMQ: PHY[5] MII transmit bit 3. RQ: no connection for RMII. MQ/FMQ: PHY[5] MII transmit bit 2. RQ: no connection for RMII. PHY[5] MII/RMII transmit bit 1. PHY[5] MII/RMII transmit bit 0. MQ/FMQ: PHY[5] MII transmit error. RQ: no connection for RMII. MQ/FMQ: Output PHY[5] MII transmit clock RQ: Input PHY[5] RMII reference clock, 50MHz 50ppm, the 50MHz clock comes from PMRXC Pin 60. Digital ground. 3.3V, 2.5V or 1.8V digital VDD for digital I/O circuitry. MQ/FMQ: Output PHY[5] MII receive clock. RQ: Output PHY[5] RMII reference clock, this clock is used when opposite doesn't provide RMII 50MHz clock or the system doesn't provide an external 50MHz clock for the P5-RMII interface. MQ/FMQ: PMRXDV is for PHY[5] MII receive data valid. RQ: PMCRSDV is for PHY[5] RMII Carrier Sense/Receive Data Valid Output.
5
61
PMRXDV/PMCRSDV
IPD/O
5
January 2011
15
M9999-012011-1.2
Micrel, Inc.
KSZ8895MQ/RQ/FMQ
Pin Number
Pin Name
Type
(1)
Port
Pin Function
(2)
MQ/FMQ: PHY[5] MII receive bit 3. RQ: no connection for RMII 62 PMRXD3 IPD/O 5 Strap option: PD (default) = enable flow control. PU = disable flow control. MQ/FMQ: PHY[5] MII receive bit 2. RQ: no connection for RMII. 63 PMRXD2 IPD/O 5 Strap option: PD (default) = disable back pressure. PU = enable back pressure. PHY[5] MII/RMII receive bit 1. 64 PMRXD1 IPD/O 5 Strap option: PD (default) = drop excessive collision packets. PU = does not drop excessive collision packets. PHY[5] MII/RMII receive bit 0. Strap option: 65 PMRXD0 IPD/O 5 PD (default) = disable aggressive back-off algorithm in half-duplex mode. PU = enable for performance enhancement. MQ/FMQ:PHY[5] MII receive error RQ: no connection for RMII 66 PMRXER IPD/O 5 Strap option: PD (default) = packet size 1518/1522 bytes. PU = 1536 bytes. MQ/FMQ: PHY[5] MII carrier sense. RQ: no connection for RMII. Strap option for port 4 only. 67 PCRS IPD/O 5 PD (default) = force half-duplex if auto-negotiation is disabled or fails. PU = force full-duplex if auto negotiation is disabled or fails. Refer to Register 76. MQ/FMQ: PHY[5] MII collision detect. RQ: no connection. 68 PCOL IPD/O 5 Strap option for port 4 only. PD (default) = no force flow control, normal operation. PU = force flow control. Refer to Register 66. 69 70 SMTXEN SMTXD3 IPD IPD Port 5 Switch MII/RMII transmit enable. MQ/FMQ: Port 5 Switch MII transmit bit 3. RQ: no connection for RMII.
January 2011
16
M9999-012011-1.2
Micrel, Inc.
KSZ8895MQ/RQ/FMQ
Pin Number 71 72 73 74
Pin Name SMTXD2 SMTXD1 SMTXD0 SMTXER
Type
(1)
Port
IPD IPD IPD IPD
Pin Function MQ/FMQ: Port 5 Switch MII transmit bit 2. RQ: no connection for RMII. Port 5 Switch MII/RMII transmit bit 1. Port 5 Switch MII/RMII transmit bit 0. MQ/FMQ: Port 5 Switch MII transmit error. RQ: no connection for RMII. MQ/FMQ: Port 5 Switch MII transmit clock, Input: SW5-MII MAC mode, Output: SW5-MII PHY modes. RQ: Input SW5-RMII 50MHz +/-50ppm reference clock. The 50MHz clock comes from SMRXC Pin 78 when the device is the clock mode which the device's clock comes from 25MHz crystal/oscillator from pins X1/X2. Or the 50MHz clock comes from external 50MHz clock source when the device is the normal mode which the device's clock source comes from SMTXC pin not from X1/X2 pins. Digital ground. 3.3V, 2.5V or 1.8V digital VDD for digital I/O circuitry. MQ/FMQ: Port 5 Switch MII receive clock, Input: SW5-MII MAC mode, Output: SW5-MII PHY mode. RQ: Output SW5-RMII 50MHz clock, this clock is used when opposite doesn't provide RMII reference clock or the system doesn't provide an external 50MHz clock for the RMII interface. MQ/FMQ: SMRXDV is for Switch MAC5 MII receive data valid. RQ: SMCRSDV is for MAC5 RMII Carrier Sense/Receive Data Valid Output. MQ/FMQ: Port 5 Switch MII receive bit 3. RQ: no connection for RMII Strap option: PD (default) = Disable Switch SW5-MII full-duplex flow control PU = Enable Switch SW5-MII full-duplex flow control. MQ/FMQ: Port 5 Switch MII receive bit 2. RQ: no connection for RMII Strap option: PD (default) = Switch SW5-MII in full-duplex mode; PU = Switch SW5-MII in half-duplex mode.
(2)
75
SMTXC/SMREFCLK
I/O
76 77
GNDD VDDIO
GND P
78
SMRXC
I/O
79
SMRXDV/SMCRSDV
IPD/O
80
SMRXD3
IPD/O
81
SMRXD2
IPD/O
January 2011
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M9999-012011-1.2
Micrel, Inc.
KSZ8895MQ/RQ/FMQ
Pin Number 82
Pin Name SMRXD1
Type
(1)
Port
IPD/O
83
SMRXD0
IPD/O
84 85
SCOL SCRS
IPD/O IPD/O
Pin Function Port 5 Switch MII/RMII receive bit 1. Strap option: PD (default) = Port 5 Switch SW5-MII in 100Mbps mode. PU = Switch SW5-MII in 10Mbps mode. Port 5 Switch MII/RMII receive bit 0. Strap option: LED mode PD (default) = mode 0; PU = mode 1. See "Register 11." Mode 0, link at: 100/Full LEDx[2,1,0] = 0, 0, 0 100/Half LEDx[2,1,0] = 0, 1, 0 10/Full LEDx[2,1,0] = 0, 0, 1 10/Half LEDx[2,1,0] = 0, 1, 1 Mode 1, link at: 100/Full LEDx[2,1,0] = 0, 1, 0 100/Half LEDx[2,1,0] = 0, 1, 1 10/Full LEDx[2,1,0] = 1, 0, 0 10/Half LEDx[2,1,0] = 1, 0, 1 Mode 0 Mode 1 LEDX_2 Lnk/Act 100Lnk/Act LEDX_1 Fulld/Col 10Lnk/Act LEDX_0 Speed Full duplex MQ/FMQ: Port 5 Switch MII collision detect, Input: SW5-MII MAC modes, Output: SW5-MII PHY modes. RQ: no connection for RMII MQ/FMQ: Port 5 Switch MII modes carrier sense, Input: SW5-MII MAC modes, Output: SW5-MII PHY modes. RQ: no connection for RMII Pins 91, 86, and 87 are dual MII/RMII configuration pins for the Port 5 MAC5 MII/RMII and PHY[5] MII/RMII. SW5-MII supports both MAC mode and PHY modes. P5-MII supports PHY mode only. See pins configuration below. Port 5 Switch MAC5 SW5MII/RMII Disable, Otri PHY Mode MII, or RMII MAC Mode MII, or RMII PHY Mode SNI Disable PHY Mode MII or RMII MAC Mode MII or RMII PHY Mode SNI
(2)
Pin# (91, 86, 87) 000 86 SCONF1 IPD 001 010 011 100 101 110 111
Port5 PHY5 P5- MII/RMII Disable, Otri Disable, Otri Disable, Otri Disable, Otri Disable P5-MII/RMII P5-MII/RMII P5-MII/RMII
January 2011
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M9999-012011-1.2
Micrel, Inc.
KSZ8895MQ/RQ/FMQ
Pin Number 87 88 89
Pin Name SCONF0 GNDD VDDC
Type
(1)
Port
Pin Function
(2)
IPD GND P
Dual MII/RMII configuration pin. See pin 86 descriptions. Digital ground. 1.2V digital core VDD. LED indicator 2. Strap option: Aging setup. See "Aging" section. PU (default) = aging enable PD = aging disable. LED indicator 1. Strap option: PU (default): enable PHY[5] MII I/F. PD: tristate all PHY[5] MII output. See "Pin 86 SCONF1." LED indicator 0. Strap option for port 4 only. PU (default) = Enable auto-negotiation. PD = Disable auto-negatiation. Strap to register76 bit[7]. LED indicator 2. LED indicator 1. LED indicator 0. Strap option: PU (default) = Normal mode. PD = Energy Detection mode (EDPD mode) Strap to register 14 bits[4:3] LED indicator 2. LED indicator 1. LED indicator 0. Strap option: PU (default) = Select I/O drive strength (8mA); PD = Select I/O drive strength (12mA). Strap to register132 bit[7-6]. Digital ground. 3.3V, 2.5V or 1.8V digital VDD for digital I/O circuitry. LED indicator 2. Strap option for RQ only: PU (default) = Select the device as clock mode in SW5- RMII, 25MHz crystal/oscillator to X1/X2 pins of the device and pins of SMRXC and PMRXC output 50MHz clock. PD = Select the device as normal mode in SW5-RMII. Switch MAC5 used only. The input clock from X1/X2 pins is not used, the device's clock source comes from SMTXC/SMREFCLK pin which the 50MHz reference clock comes from external 50MHz clock source, PMRXC can output 50MHz clock for P5-RMII interface in the normal mode. LED indicator 1. Strap option: for Port 3 only. PU (default) = Enable auto-negotiation. PD = Disable auto-negatiation. Strap to register60 bit[7]. LED indicator 0. LED indicator 2.
90
LED5-2
IPU/O
5
91
LED5-1
IPU/O
5
92 93 94
LED5-0 LED4-2 LED4-1
IPU/O IPU/O IPU/O
5 4 4
95
LED4-0
IPU/O
4
96 97
LED3-2 LED3-1
IPU/O IPU/O
3 3
98
LED3-0
IPU/O
3
99 100
GNDD VDDIO
GND P
101
LED2-2
IPU/O
2
102 103 104
LED2-1 LED2-0 LED1-2
IPU/O IPU/O IPU/O
2 2 1
January 2011
19
M9999-012011-1.2
Micrel, Inc.
KSZ8895MQ/RQ/FMQ
Pin Number 105
Pin Name LED1-1
Type
(1)
Port 1
IPU/O
106
LED1-0
IPU/O
1
107
MDC
IPU
All
108
MDIO
I/O
All
Pin Function LED indicator 1. Strap option: for port 3 only. PU (default) = no force flow control, normal operation. PD = force flow control. Strap to register60 bit[4]. LED indicator 0. Strap option for port 3 only. PU (default) = force half-duplex if auto-negotiation is disabled or fails. PD = force full-duplex if auto negotiation is disabled or fails. Strap to register60 bit[5]. Switch or PHY[5] MII management (MIIM registers) data clock. Or SMI interface clock Switch or PHY[5] MII management (MIIM registers) data I/O. Or SMI interface data I/O. Features internal pull down to define pin state when not driven. Need an external pull-up when driven. SPI serial data output in SPI slave mode. (1) Input clock up to 25MHz in SPI slave mode, (2) output clock at 61kHz in I C master mode. See "Pin 113." (1) Serial data input in SPI slave mode; (2) serial data input/output in I C master mode. See "Pin 113." Active low. (1) SPI data transfer start in SPI slave mode. When SPIS_N is high, the KSZ8895MQ/RQ/FMQ/RQ/FMQ is deselected and SPIQ is held in high impedance state, a high-to-low transition to initiate the SPI data transfer. (2) not used in I C master mode. Serial bus configuration pin. For this case, if the EEPROM is not present, the KSZ8895MQ/RQ/FMQ/RQ/FMQ will start itself with the PS[1.0] = 00 default register values.
2 2 2
(2)
109 110 111
SPIQ SPIC/SCL SSPID/SDA
OTRI I/O I/O
All All All
112
SPIS_N
IPU
All
113
PS1
IPD
Pin Configuration PS[1.0]=00 PS[1.0]=01 PS[1.0]=10 PS[1.0]=11
Serial Bus Configuration I C Master Mode for EEPROM SMI Interface Mode SPI Slave Mode for CPU Interface Factory Test Mode (BIST)
2
114 115 116 117 118 119
PS0 RST_N GNDD VDDC TESTEN SCANEN
IPD IPU GND P IPD IPD
Serial bus configuration pin. See "Pin 113." Reset the KSZ8895MQ/RQ/FMQ/RQ/FMQ device. Active low. Digital ground. 1.2V digital core VDD. NC for normal operation. Factory test pin. NC for normal operation. Factory test pin.
January 2011
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M9999-012011-1.2
Micrel, Inc.
KSZ8895MQ/RQ/FMQ
Pin Number 120 121 122 123 124 125 126 127 128
Pin Name NC X1 X2 NC NC LDO_O IN_PWR_SEL GNDA TEST2
Type NC I O NC NC P
(1)
Port
Pin Function No connect.
(2)
25MHz crystal clock connection/or 3.3V Oscillator input. Crystal/Oscillator should be 50ppm tolerance. 25MHz crystal clock connection. No connect. No connect. When pin126 is pull-up, the Internal 1.2V LDO controller is enabled and create 1.2V output with using an external FET. When pin126 is pull-down (default), the pin 125 is tristated. Pull-up to enable LDO_O of pin 125. Pull-down to disable LDO_0. Analog ground. NC for normal operation. Factory test pin.
IPD GND NC
Notes: 1. P = Power supply. I = Input. O = Output. I/O = Bidirectional. GND = Ground. IPU = Input w/internal pull-up. IPD = Input w/internal pull-down. IPD/O = Input w/internal pull-down during reset, output pin otherwise. IPU/O = Input w/internal pull-up during reset, output pin otherwise. NC = No connect. 2. PU = Strap pin pull-up. PD = Strap pull-down. OTRI = Output tristated.
January 2011
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M9999-012011-1.2
Micrel, Inc.
KSZ8895MQ/RQ/FMQ
Pin for Strap-in Options
The KSZ8895MQ/RQ/FMQ can function as a managed switch or unmanaged switch. If no EEPROM or microcontroller exists, then the KSZ8895MQ/RQ/FMQ will operate from its default setting. The strap-in option pins can be configured by external pull-up/down resistors and take the effect after power down reset or warm reset, the functions are described in the table below.
Pin # 1 Pin Name MDI-XDIS PU/PD Ipd
(1)
Description
(1)
62
PMRXD3
Ipd/O
63
PMRXD2
Ipd/O
64
PMRXD1
Ipd/O
65
PMRXD0
Ipd/O
66
PMRXER
Ipd/O
67
PCRS
Ipd/O
68
PCOL
Ipd/O
80
SMRXD3
Ipd/O
81
SMRXD2
Ipd/O
82
SMRXD1
Ipd/O
Disable auto MDI/MDI-X. Strap option: PD = (default) = normal operation. PU = disable auto MDI/MDI-X on all ports. PHY[5] MII receive bit 3. Strap option: PD (default) = enable flow control; PU = disable flow control. PHY[5] MII receive bit 2. Strap option: PD (default) = disable back pressure; PU = enable back pressure. PHY[5] MII receive bit 1. Strap option: PD (default) = drop excessive collision packets; PU = does not drop excessive collision packets. PHY[5] MII receive bit 0. Strap option: PD (default) = disable aggressive back-off algorithm in half-duplex mode; PU = enable for performance enhancement. PHY[5] MII receive error. Strap option: PD (default) = 1522/1518 bytes; PU = packet size up to 1536 bytes. PHY[5] MII carrier sense Strap option for Port 4 only. PD (default) = force half-duplex if auto-negotiation is disabled or fails. PU = force full-duplex if auto-negotiation is disabled or fails. Refer to register 76. PHY[5] MII collision detect Strap option for Port 4 only. PD (default) = no force flow control. PU = force flow control. Refer to register 66. Switch MII receive bit 3. Strap option: PD (default) = disable switch SW5-MII full-duplex flow control; PU = enable switch SW5-MII full-duplex flow control. Switch MII receive bit 2. Strap option: PD (default) = switch SW5-MII in full-duplex mode; PU = switch SW5-MII in half-duplex mode. Switch MII receive bit 1. Strap option: PD (default) = switch SW5-MII in 100Mbps mode. PU = switch MII in 10Mbps mode.
January 2011
22
M9999-012011-1.2
Micrel, Inc.
Pin # 83 Pin Name SMRXD0 PU/PD
(1)
KSZ8895MQ/RQ/FMQ
Description
(1)
Ipd/O
Switch MII receive bit 0. Strap option: LED mode PD (default) = mode 0; PU = mode 1. See "Register 11." Mode 0 Mode 1 LEDX_2 LEDX_1 LEDX_0 Lnk/Act Fulld/Col Speed 100Lnk/Act 10Lnk/Act Fulld
86
SCONF1
Ipd
Pin 91,86,87 are dual MII/RMII configuration pins for the Port 5 MAC 5 MII/RMII and PHY[5] MII/RMII. SW5-MII supports both MAC mode and PHY modes. P5MII supports PHY mode only. See pins configuration below. Pins [91, 86, 87] Port 5 MAC 5 Switch Port 5 PHY [5] SW5-MII MII/RMII P5-MII/RMII 000 Disable, Otri Disable, Otri 001 010 011 100 101 110 111 PHY Mode MII or RMII MAC Mode MII or RMII PHY Mode SNI Disable PHY Mode MII or RMII MAC Mode MII or RMII PHY Mode SNI Disable, Otri Disable, Otri Disable, Otri Disable P5- MII/RMII P5- MII/RMII P5- MII/RMII
87 90
SCONF0 LED5-2
Ipd Ipu/O
Dual MII/RMII configuration pin. See pin 86 description. LED5 indicator 2. Strap option: Aging setup. See "Aging" section PU (default) = aging enable; PD = aging disable. LED5 indicator 1. Strap option: PU (default): enable PHY[5] MII I/F. PD: tristate all PHY[5] MII output. See "Pin 86 SCONF1." LED5 indicator 0. Strap option for Port 4 only. PU (default) = Enable auto-negotiation. PD = Disable auto-negatiation. Strap to register76 bit[7]. LED indicator 0. Strap option: PU (default) = Normal mode. PD = Energy Detection mode (EDPD mode). Strap to register 14 bits[4:3]. LED3 indicator 0. Strap option: PU (default) = Select I/O current drive strength (8mA); PD = Select I/O current drive strength (12mA). Strap to register132 bit[7:6].
91
LED5-1
Ipu/O
92
LED5-0
Ipu/O
95
LED4-0
Ipu/O
98
LED3-0
Ipu/O
January 2011
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M9999-012011-1.2
Micrel, Inc.
Pin # Pin Name PU/PD
(1)
KSZ8895MQ/RQ/FMQ
Description
(1)
101
LED2-2
Ipu/O
102
LED2-1
Ipu/O
LED2 indicator 2. Strap option for KSZ8895RQ only: PU (default) = Select the device as clock mode in RQ SW5- RMII, 25MHz crystal to X1/X2 pins of the device and REFCLK output 50MHz clock. PD = Select the device as normal mode in SW5-RMII. Switch MAC5 used only. The input clock is useless from X1/X2 pin, the device's clock comes from SMTXC/SMREFCLK pin, 50MHz reference clock from external 50MHz clock source. LED2 indicator 1. Strap option for Port 3 only. PU (default) = Enable auto-negotiation. PD = Disable auto-negatiation. Strap to register60 bit[7]. LED2 indicator 0. LED1 indicator 2. LED1 indicator 1. Strap option for Port 3 only. PU (default) = no force flow control, normal operation. PD = force flow control. Strap to register50 bit[4]. LED1 indicator 0. Strap option for Port 3 only. PU (default) = force half-duplex if auto-negotiation is disabled or fails. PD = force full-duplex if auto negotiation is disabled or fails. Strap to register60 bit[5]. Serial bus configuration pin. For this case, if the EEPROM is not present, the KSZ8895MQ/RQ/FMQ/RQ/FMQ will start itself with the PS[1:0] =00 default register values . Pin Configuration Serial Bus Configuration PS[1:0]=00 PS[1:0]=01 PS[1:0]=10 PS[1:0]=11 I C Master Mode for EEPROM SMI Interface Mode SPI Slave Mode for CPU Interface Factory Test Mode (BIST)
2
103 104 105
LED2-0 LED1-2 LED1-1
Ipu/O Ipu/O Ipu/O
106 113
LED1-0 PS1
Ipu/O Ipd
114 128
Notes: 1.
PS0 TEST2
Ipd NC
Serial bus configuration pin. See "Pin 113." NC for normal operation. Factory test pin.
NC = No connect. Ipd = Input w/internal pull-down. Ipd/O = Input w/internal pull-down during reset, output pin otherwise. Ipu/O = Input w/internal pull-up during reset, output pin otherwise.
January 2011
24
M9999-012011-1.2
Micrel, Inc.
KSZ8895MQ/RQ/FMQ
Introduction
The KSZ8895MQ/RQ/FMQ contains five 10/100 physical layer transceivers and five media access control (MAC) units with an integrated Layer 2 managed switch. The device runs in three modes. The first mode is as a five-port integrated switch. The second is as a five-port switch with the fifth port decoupled from the physical port. In this mode, access to the fifth MAC is provided through a media independent interface (MII/RMII). This is useful for implementing an integrated broadband router. The third mode uses the dual MII/RMII feature to recover the use of the fifth PHY. This allows the additional broadband gateway configuration, where the fifth PHY may be accessed through the P5-MII/RMII port. The KSZ8895MQ/RQ/FMQ have the flexibility to reside in a managed or unmanaged design. In a managed design, a host processor has complete control of the KSZ8895MQ/RQ/FMQ via the SPI bus, or the MDC/MDIO interface. An unmanaged design is achieved through I/O strapping or EEPROM programming at system reset time. On the media side, the KSZ8895MQ/RQ/FMQ supports IEEE 802.3 10BASE-T, 100BASE-TX on all copper ports with Auto MDI/MDIX. The KSZ8895FMQ supports 100BASE-FX on port 3 and port 4. The KSZ8895MQ/RQ/FMQ can be used as fully managed 5-port switch or hook up to microprocessor by its SW-MII/RMII interfaces for any application solutions. Physical signal transmission and reception are enhanced through the use of patented analog circuitry that makes the design more efficient and allows for lowest power consumption and smaller chip die size. There are a number of major enhancements from the KS8895MA/FQ to the KSZ8895MQ/FMQ. These include: more host interface options, a dual Switch MAC5 MII and PHY5 MII interfaces with other options, RMII from part of the KSZ8895RQ, tag as well as port based VLAN, rapid spanning tree support, IGMP snooping support, port mirroring support and more flexible rate limiting and new filtering functionality.
Functional Overview: Physical Layer Transceiver
100BASE-TX Transmit The 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI conversion, MLT3 encoding and transmission. The circuit starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125MHz serial bit stream. The data and control stream is then converted into 4B/5B coding followed by a scrambler. The serialized data is further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output. The output current is set by an external 1% 12.4k resistor for the 1:1 transformer ratio. It has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude balance, overshoot, and timing jitter. The wave-shaped 10BASE-T output is also incorporated into the 100BASE-TX transmitter. 100BASE-TX Receive The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion. The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted pair cable. Since the amplitude loss and phase distortion is a function of the length of the cable, the equalizer has to adjust its characteristics to optimize the performance. In this design, the variable equalizer will make an initial estimation based on comparisons of incoming signal strength against some known cable characteristics, then tunes itself for optimization. This is an ongoing process and can self-adjust against environmental changes such as temperature variations. The equalized signal then goes through a DC restoration and data conversion block. The DC restoration circuit is used to compensate for the effect of baseline wander and improve the dynamic range. The differential data conversion circuit converts the MLT3 format back to NRZI. The slicing threshold is also adaptive. The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used to convert the NRZI signal into the NRZ format. The signal is then sent through the de-scrambler followed by the 4B/5B decoder. Finally, the NRZ serial data is converted to the MII format and provided as the input data to the MAC.
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PLL Clock Synthesizer The KSZ8895MQ/RQ/FMQ generates 125MHz, 83MHz, 41MHz, 25MHz and 10MHz clocks for system timing. Internal clocks are generated from an external 25MHz crystal or oscillator. Scrambler/De-Scrambler (100BASE-TX only) The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce EMI and baseline wander. The data is scrambled through the use of an 11-bit wide linear feedback shift register (LFSR). This can generate a 2047-bit non-repetitive sequence. The receiver will then de-scramble the incoming data stream with the same sequence at the transmitter. 100BASE-FX Operation 100BASE-FX operation is very similar to 100BASE-TX operation except that the scrambler/de-scrambler and MLT3 encoder/decoder are bypassed on transmission and reception. In this mode, the auto-negotiation feature is bypassed since there is no standard that supports fiber auto-negotiation. 100BASE-FX Signal Detection The physical port runs in 100BASE-FX fiber mode for the Port 3 and Port 4 of the KSZ8895FMQ. This signal is internally referenced to 1.2V. The fiber module interface should be set by a voltage divider such that FXSDx `H' is above this 1.2V reference, indicating signal detect, and FXSDx `L' is below the 1.2V reference to indicate no signal. There is no auto-negotiation for 100BASE-FX mode, the ports must be forced to either full or half-duplex for the fiber ports. Note that strap-in options support Port 3 and Port 4 to disable Auto-negotiation, force 100Base-FX speed, force duplex mode and force flow control for KSZ8895FMQ with unmanaged mode. 100BASE-FX far End fault far end fault occurs when the signal detection is logically false from the receive fiber module. When this occurs, the transmission side signals the other end of the link by sending 84 1s followed by a zero in the idle period between frames. The far end fault may be disabled through register settings. 10BASE-T Transmit The output 10BASE-T driver is incorporated into the 100BASE-T driver to allow transmission with the same magnetics. They are internally wave-shaped and pre-emphasized into outputs with a typical 2.3V amplitude. The harmonic contents are at least 27dB below the fundamental when driven by an all-ones Manchester-encoded signal. 10BASE-T Receive On the receive side, input buffer and level detecting squelch circuits are employed. A differential input receiver circuit and a PLL perform the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data. A squelch circuit rejects signals with levels less than 400mV or with short pulsewidths in order to prevent noises at the RXP or RXM input from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming signal and the KSZ8895MQ/RQ/FMQ decodes a data frame. The receiver clock is maintained active during idle periods in between data reception. MDI/MDI-X Auto Crossover To eliminate the need for crossover cables between similar devices, the KSZ8895MQ/RQ/FMQ supports HP Auto MDI/MDI-X and IEEE 802.3u standard MDI/MDI-X auto crossover. HP Auto MDI/MDI-X is the default. The auto-sense function detects remote transmit and receive pairs and correctly assigns transmit and receive pairs for the KSZ8895MQ/RQ/FMQ device. This feature is extremely useful when end users are unaware of cable types, and also, saves on an additional uplink configuration connection. The auto-crossover feature can be disabled through the port control registers, or MIIM PHY registers. The IEEE 802.3u standard MDI and MDI-X definitions are:
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MDI RJ-45 Pins 1 2 3 6 Signals TD+ TDRD+ RDRJ-45 Pins 1 2 3 6
MDI-X Signals RD+ RDTD+ TD-
Table 1. MDI/MDI-X Pin Definitions
Straight Cable A straight cable connects an MDI device to an MDI-X device, or an MDI-X device to an MDI device. The following diagram depicts a typical straight cable connection between a NIC card (MDI) and a switch, or hub (MDI-X).
10/100 Ethernet Media Dependent Interface
10/100 Ethernet Media Dependent Interface
1 Transmit Pair 2 3 4 Receive Pair 5 6 7 8 Straight Cable
1 Receive Pair 2 3 4 Transmit Pair 5 6 7 8
Modular Connector (RJ-45) NIC
Modular Connector (RJ-45) HUB (Repeater or Switch)
Figure 1. Typical Straight Cable Connection
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Crossover Cable A crossover cable connects an MDI device to another MDI device, or an MDI-X device to another MDI-X device. The following diagram shows a typical crossover cable connection between two switches or hubs (two MDI-X devices).
10/100 Ethernet Media Dependent Interface 10/100 Ethernet Media Dependent Interface
1 Receive Pair 2 3 4 Transmit Pair 5 6 7 8
Crossover Cable
1 Receive Pair 2 3 4 Transmit Pair 5 6 7 8
Modular Connector (RJ-45) HUB (Repeater or Switch)
Modular Connector (RJ-45) HUB (Repeater or Switch)
Figure 2. Typical Crossover Cable Connection
Auto-Negotiation The KSZ8895MQ/RQ/FMQ conforms to the auto-negotiation protocol as described by the 802.3 committee. Autonegotiation allows unshielded twisted pair (UTP) link partners to select the highest common mode of operation. Link partners advertise their capabilities to each other, and then compare their own capabilities with those they received from their link partners. The highest speed and duplex setting that is common to the two link partners is selected as the mode of operation. Auto-negotiation is supported for the copper ports only. The following list shows the speed and duplex operation mode from highest to lowest. * Highest: 100Base-TX, full-duplex * High: * Low: 100Base-TX, half-duplex 10Base-T, full-duplex
* Lowest: 10Base-T, half-duplex If auto-negotiation is not supported or the KSZ8895MQ/RQ/FMQ link partner is forced to bypass auto-negotiation, the KSZ8895MQ/RQ/FMQ sets its operating mode by observing the signal at its receiver. This is known as parallel detection, and allows the KSZ8895MQ/RQ/FMQ to establish link by listening for a fixed signal protocol in the absence of auto-negotiation advertisement protocol. The auto-negotiation link up process is shown in the following flow chart.
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Start Auto Negotiation
Force Link Setting
N o
Parallel Operation
Yes
Bypass Auto Negotiation and Set Link Mode
Attempt Auto Negotiation
Listen for 100BASE-TX Idles
Listen for 10BASE-T Link Pulses
No
Join Flow
Link Mode Set ?
Yes
Link Mode Set
Figure 3. Auto-Negotiation
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On-chip Termination Resistors The KSZ8895MQ/RQ/FMQ reduces the board cost and simplifies the board layout by using on-chip termination resistors for all ports and RX/TX differential pairs without the external termination resistors. The solution of the on chip termination and internal biasing will save about 500 to 1000mw power consumption in system level compare with regular using external biasing and termination resistors, and the transformer will not consume power any more. And the center tap of the transformer doesn't need to be tied to the analog power and do not tie the center taps together between RX and TX pairs for its application. Internal 1.2V LDO Controller The KSZ8895MQ/RQ/FMQ reduces board cost and simplifies board layout by integrating an internal 1.2V LDO controller to drive a low cost MOSFET to supply the 1.2V core power voltage for a single 3.3V power supply solution. The internal 1.2V LDO controller can be disabled by the pin 126 IN_PWR_SEL pull-down if want to use an external 1.2V LDO.
Functional Overview: Power Management
The KSZ8895MQ/RQ/FMQ supports a full chip hardware power down mode. When activated low, internally the PWRDN pin 47 (pin PWRDN =0), the entire chip is powered down. If this pin is de-asserted, the chip will be internal reset. The KSZ8895MQ/RQ/FMQ can also use multiple power level of 3.3V, 2.5V or 1.8V for VDDIO to support different I/O voltage. The KSZ8895MQ/RQ/FMQ supports enhanced power management feature in low power state with energy detection to ensure low-power dissipation during device idle periods. There are five operation modes under the power management function which is controlled by the Register 14 bit [4:3] and the Port Register Control 13 bit3 as shown below: Register 14 bit [4:3] = 00 Normal Operation Mode Register 14 bit [4:3] = 01 Energy Detect Mode Register 14 bit [4:3] = 10 Soft Power Down Mode Register 14 bit [4:3] = 11 Power Saving Mode The Port Register 29, 45, 61, 77, 93 Control 13 bit 3 =1 are for the Port Based Power-Down Mode. Table 2 indicates all internal function blocks status under four different power management operation modes.
KSZ8895MQ/RQ/FMQ Function Blocks Internal PLL Clock Tx/Rx PHY MAC Host Interface Power Management Operation Modes Normal Mode Enabled Enabled Enabled Enabled Power Saving Mode Enabled Rx unused block disabled Enabled Enabled Energy Detect Mode Disabled Energy detect at Rx Disabled Disabled Soft Power Down Mode Disabled Disabled Disabled Disabled
Table 2. Internal Function Block Status
Normal Operation Mode This is the default setting bit [4:3] =00 in register 14 after the chip power-up or hardware reset. When KSZ8895MQ/RQ/FMQ is in this normal operation mode, all PLL clocks are running, PHY and MAC are on and the host interface is ready for CPU read or write. During the normal operation mode, the host CPU can set the bit [4:3] in register 14 to transit the current normal operation mode to any one of the other three power management operation modes.
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Energy Detect Mode The energy detect mode provides a mechanism to save more power than in the normal operation mode when the KSZ8895MQ/FMQ port is not connected to an active link partner. In this mode, the device will save more power when the cables are plugged out. If the cable is not plugged, the device can automatically enter to a low power state, i.e., the energy detect mode. In this mode, the device will keep transmitting 120ns width pulses at 1 pulse/s rate. Once activity resumes due to plugging a cable or attempting by the far end to establish link, the device can automatically power up to normal power state in energy detect mode. Energy detect mode consists of two states, normal power state and low power state. While in low power state, the device reduces power consumption by disabling all circuitry except the energy detect circuitry of the receiver. The energy detect mode is entered by setting bit [4:3] =01 in register 14. When the KSZ8895MQ/FMQ is in this mode, it will monitor the cable energy. If there is no energy on the cable for a time longer than pre-configured value at bit [7:0] Go-Sleep time in register 15, KSZ8895MQ/FMQ will go into a low power state. When KSZ8895MQ/FMQ is in low power state, it will keep monitoring the cable energy. Once the energy is detected from the cable, The device will enter normal power state. When the device is at normal power state, it is able to transmit or receive packet from the cable. Soft Power Down Mode The soft power down mode is entered by setting bit [4:3] =10 in register 14. When KSZ8895MQ/RQ/FMQ is in this mode, all PLL clocks are disabled, also all of PHYs and the MACs are off. Any dummy host access will wake-up this device from current soft power down mode to normal operation mode and internal reset will be issued to make all internal registers go to the default values. Power Saving Mode The power saving mode is entered when auto-negotiation mode is enabled, cable is disconnected, and by setting bit [4:3] =11 in register 14. When KSZ8895MQ/RQ/FMQ is in this mode, all PLL clocks are enabled, MAC is on, all internal registers value will not change, and host interface is ready for CPU read or write. In this mode, it mainly controls the PHY transceiver on or off based on line status to achieve power saving. The PHY remains transmitting and only turns off the unused receiver block. Once activity resumes due to plugging a cable or attempting by the far end to establish link, the KSZ8895MQ/RQ/FMQ can automatically enabled the PHY power up to normal power state from power saving mode. During this power saving mode, the host CPU can set bit [4:3] in register 14 to transit the current power saving mode to any one of the other three power management operation modes. Port based Power Down Mode In addition, the KSZ8895MQ/RQ/FMQ features a per-port power down mode. To save power, a PHY port that is not in use can be powered down via the port registers control 13 bit3, or MIIM PHY registers 0 bit11.
Functional Overview: Switch Core
Address Look-Up The internal look-up table stores MAC addresses and their associated information. It contains a 1K unicast address table plus switching information. The KSZ8895MQ/RQ/FMQ is guaranteed to learn 1K addresses and distinguishes itself from a hash-based look-up table, which depending on the operating environment and probabilities, may not guarantee the absolute number of addresses it can learn. Learning The internal look-up engine updates its table with a new entry if the following conditions are met: * The received packet's source address (SA) does not exist in the look-up table. * The received packet is good; the packet has no receiving errors and is of legal length. The look-up engine inserts the qualified SA into the table, along with the port number and time stamp. If the table is full, the last entry of the table is deleted first to make room for the new entry.
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Migration The internal look-up engine also monitors whether a station is moved. If this occurs, it updates the table accordingly. Migration happens when the following conditions are met: * The received packet's SA is in the table but the associated source port information is different. * The received packet is good; the packet has no receiving errors and is of legal length. The look-up engine will update the existing record in the table with the new source port information. Aging The look-up engine will update the time stamp information of a record whenever the corresponding SA appears. The time stamp is used in the aging process. If a record is not updated for a period of time, the look-up engine will remove the record from the table. The look-up engine constantly performs the aging process and will continuously remove aging records. The aging period is 300 +/- 75 seconds. This feature can be enabled or disabled through Register 3 or by external pull-up or pull-down resistors on LED[5][2]. See "Register 3" section. Forwarding The KSZ8895MQ/RQ/FMQ will forward packets using an algorithm that is depicted in the following flowcharts. Figure 6 shows stage one of the forwarding algorithm where the search engine looks up the VLAN ID, static table, and dynamic table for the destination address, and comes up with "port to forward 1" (PTF1). PTF1 is then further modified by the spanning tree, IGMP snooping, port mirroring, and port VLAN processes to come up with "port to forward 2" (PTF2), as shown in Figure 7. This is where the packet will be sent. KSZ8895MQ/RQ/FMQ will not forward the following packets: * Error packets. These include framing errors, FCS errors, alignment errors, and illegal size packet errors. * 802.3x pause frames. The KSZ8895MQ/RQ/FMQ will intercept these packets and perform the appropriate actions. * "Local" packets. Based on destination address (DA) look-up. If the destination port from the look-up table matches the port where the packet was from, the packet is defined as "local." Switching Engine The KSZ8895MQ/RQ/FMQ features a high-performance switching engine to move data to and from the MAC's, packet buffers. It operates in store and forward mode, while the efficient switching mechanism reduces overall latency. The KSZ8895MQ/RQ/FMQ has a 64kB internal frame buffer. This resource is shared between all five ports. There are a total of 512 buffers available. Each buffer is sized at 128B. Media Access Controller (MAC) Operation The KSZ8895MQ/RQ/FMQ strictly abides by IEEE 802.3 standards to maximize compatibility. Inter-Packet Gap (IPG) If a frame is successfully transmitted, the 96-bit time IPG is measured between the two consecutive MTXEN. If the current packet is experiencing collision, the 96-bit time IPG is measured from MCRS and the next MTXEN. Backoff Algorithm The KSZ8895MQ/RQ/FMQ implements the IEEE Std. 802.3 binary exponential back-off algorithm, and optional "aggressive mode" back off. After 16 collisions, the packet will be optionally dropped depending on the chip configuration in Register 3. See "Register 3." Late Collision If a transmit packet experiences collisions after 512-bit times of the transmission, the packet will be dropped. Illegal Frames The KSZ8895MQ/RQ/FMQ discards frames less than 64 bytes and can be programmed to accept frames up to 1536 bytes in Register 4. For special applications, the KSZ8895MQ/RQ/FMQ can also be programmed to accept frames up to 1916 bytes in Register 4. Since the KSZ8895MQ/RQ/FMQ supports VLAN tags, the maximum sizing is adjusted when these tags are present.
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Flow Control The KSZ8895MQ/RQ/FMQ supports standard 802.3x flow control frames on both transmit and receive sides. On the receive side, if the KSZ8895MQ/RQ/FMQ receives a pause control frame, the KSZ8895MQ/RQ/FMQ will not transmit the next normal frame until the timer, specified in the pause control frame, expires. If another pause frame is received before the current timer expires, the timer will be updated with the new value in the second pause frame. During this period (being flow controlled), only flow control packets from the KSZ8895MQ/RQ/FMQ will be transmitted. On the transmit side, the KSZ8895MQ/RQ/FMQ has intelligent and efficient ways to determine when to invoke flow control. The flow control is based on availability of the system resources, including available buffers, available transmit queues and available receive queues. The KSZ8895MQ/RQ/FMQ flow controls a port that has just received a packet if the destination port resource is busy. The KSZ8895MQ/RQ/FMQ issues a flow control frame (XOFF), containing the maximum pause time defined in IEEE standard 802.3x. Once the resource is freed up, the KSZ8895MQ/RQ/FMQ sends out the other flow control frame (XON) with zero pause time to turn off the flow control (turn on transmission to the port). A hysteresis feature is also provided to prevent over-activation and deactivation of the flow control mechanism. The KSZ8895MQ/RQ/FMQ flow controls all ports if the receive queue becomes full.
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Start
PTF1= NULL
NO
VLAN ID Valid?
- Search VLAN table - Ingress VLAN filtering - Discard NPVID check
YES
Search complete. Get PTF1 from Static MAC Table
FOUND
Search Static Table
This search is based on DA or DA+FID
NOT FOUND Search complete. Get PTF1 from Dynamic MAC Table
FOUND
Dynamic Table Search
This search is based on DA+FID
NOT FOUND
Search complete. Get PTF1 from VLAN Table
PTF1
Figure 4. Destination Address Lookup Flow Chart, Stage 1
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PTF1
Spanning Tree Process
- Check receiving port's receive enable bit - Check destination port's transmit enable bit - Check whether packets are special (BPDU or specified)
IGMP Process
- Applied to MAC #1 to MAC #4 - MAC #5 is reserved for microprocessor - IGMP will be forwarded to port 5
Port Mirror Process
- RX Mirror - TX Mirror - RX or TX Mirror - RX and TX Mirror
Port VLAN Membership Check
PTF2
Figure 5. Destination Address Resolution Flow Chart, Stage 2
The KSZ8895MQ/RQ/FMQ will not forward the following packets: 1. Error packets These include framing errors, Frame Check Sequence (FCS) errors, alignment errors, and illegal size packet errors. 2. IEEE802.3x PAUSE frames KSZ8895MQ/RQ/FMQ intercepts these packets and performs full duplex flow control accordingly. 3. "Local" packets Based on destination address (DA) lookup, if the destination port from the lookup table matches the port from which the packet originated, the packet is defined as "local." January 2011 35
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Half-Duplex Back Pressure The KSZ8895MQ/RQ/FMQ also provides a half-duplex back pressure option (note: this is not in IEEE 802.3 standards). The activation and deactivation conditions are the same as the ones given for full-duplex mode. If back pressure is required, the KSZ8895MQ/RQ/FMQ sends preambles to defer the other station's transmission (carrier sense deference). To avoid jabber and excessive deference as defined in IEEE 802.3 standard, after a certain period of time, the KSZ8895MQ/RQ/FMQ discontinues carrier sense but raises it quickly after it drops packets to inhibit other transmissions. This short silent time (no carrier sense) is to prevent other stations from sending out packets and keeps other stations in a carrier sense deferred state. If the port has packets to send during a back pressure situation, the carrier-sense-type back pressure is interrupted and those packets are transmitted instead. If there are no more packets to send, carrier-sense-type back pressure becomes active again until switch resources are free. If a collision occurs, the binary exponential backoff algorithm is skipped and carrier sense is generated immediately, reducing the chance of further colliding and maintaining carrier sense to prevent reception of packets. To ensure no packet loss in 10BASE-T or 100BASE-TX half-duplex modes, the user must enable the following: * * Aggressive backoff (Register 3, bit 0) No excessive collision drop (Register 4, bit 3)
* Back pressure (Register 4, bit 5) These bits are not set as the default because this is not the IEEE standard. Broadcast Storm Protection The KSZ8895MQ/RQ/FMQ has an intelligent option to protect the switch system from receiving too many broadcast packets. Broadcast packets are normally forwarded to all ports except the source port and thus use too many switch resources (bandwidth and available space in transmit queues). The KSZ8895MQ/RQ/FMQ has the option to include "multicast packets" for storm control. The broadcast storm rate parameters are programmed globally and can be enabled or disabled on a per port basis. The rate is based on a 50ms interval for 100BT and a 500ms interval for 10BT. At the beginning of each interval, the counter is cleared to zeroand the rate limit mechanism starts to count the number of bytes during the interval. The rate definition is described in Registers 6 and 7. The default setting for Registers 6 and 7 is 0x4A (74 decimal). This is equal to a rate of 1%, calculated as follows: 148,800 frames/sec 50ms/interval 1% = 74 frames/interval (approx.) = 0x4A
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MII Interface Operation The media-independent interface (MII) is specified by the IEEE 802.3 committee and provides a common interface between physical layer and MAC layer devices. The KSZ8895MQ/RQ/FMQ provides two such interfaces. The P5-MII interface is used to connect to the fifth PHY, where as the SW-MII interface is used to connect to the fifth MAC. Each of these MII interfaces contains two distinct groups of signals, one for transmission and the other for receiving. Port 5 PHY 5 P5-MII/RMII Interface The media independent interface (MII) is specified by the IEEE 802.3 committee and provides a common interface between the physical layer and MAC layer devices. The Reduced Media Independent Interface (RMII) specifies a low pin count MII. The KSZ8895MQ/RQ/FMQ provides two such interfaces for MAC5 and PHY5. The Port 5 PHY5 P5MII/RMII interface is used to connect to the fifth PHY, where as the SW-MII/RMII interface is used to connect to the fifth MAC. The KSZ8895MQ/FMQ support P5-MII, the KSZ8895RQ supports P5-RMII. Each of these MII/RMII interfaces contains two distinct groups of signals, one for transmission and the other for receiving. Table 3 describes the signals used in the PHY[5] P5-MII/RMII interface. The P5-MII interface operates in PHY mode only.
MII Signal MTXEN MTXER MTXD3 MTXD2 MTXD1 MTXD0 MTXC MCOL MCRS MRXDV MRXER MRXD3 MRXD2 MRXD1 MRXD0 MRXC KSZ8895MQ/FMQ P5-MII PMTXEN PMTXER PMTXD[3] PMTXD[2] PMTXD[1] PMTXD[0] PMTXC PCOL PCRS PMRXDV PMRXER PMRXD[3] PMRXD[2] PMRXD[1] PMRXD[0] PMRXC
KSZ8895MQ/FMQ MII Signal Type
Description Transmit enable Transmit error Transmit data bit 3 Transmit data bit 2 Transmit data bit 1 Transmit data bit 0 Transmit clock Collision detection Carrier sense Receive data valid Receive error Receive data bit 3 Receive data bit 2 Receive data bit 1 Receive data bit 0 Receive clock
KSZ8895RQ P5-RMII PMTXEN
KSZ8895RQ RMII Signal Type
I I I I I I O O O O O O O O O O
I
PMTXD[1] PMTXD[0] PMREFCLK/PMTXC
I I I
PMRXDV PMRXER
O O
PMRXD[1] PMRXD[0] PMRXC
O O O
Table 3. Port 5 PHY P5-MII/RMII Signals
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Port 5 MAC 5 SW5-MII Interface for the KSZ8895MQ/FMQ Table 4 shows two connection manners, 1. The first is an external MAC connects to SW5-MII PHY mode. 2. The second is an external PHY connects to SW5-MII MAC mode. Please see the pins [91,86,87] description for detail configuration for the MAC mode and PHY mode, SW5-MII works with 25MHz clock for 100Base-TX, SW5-MII works with 2.5MHz clock for 10Base-T.
KSZ8895MQ/RQ/FMQ PHY Mode Connection External MAC MTXEN MTXER MTXD3 MTXD2 MTXD1 MTXD0 MTXC MCOL MCRS MRXDV MRXER MRXD3 MRXD2 MRXD1 MRXD0 MRXC KSZ8895MQ/RQ/FMQ SW5-MII Signals SMTXEN SMTXER SMTXD[3] SMTXD[2] SMTXD[1] SMTXD[0] SMTXC SCOL SCRS SMRXDV Not used SMRXD[3] SMRXD[2] SMRXD[1] SMRXD[0] SMRXC Type Input Input Input Input Input Input Output Output Output Output Output Output Output Output Output Output Description Transmit enable Transmit error Transmit data bit 3 Transmit data bit 2 Transmit data bit 1 Transmit data bit 0 Transmit clock Collision detection Carrier sense Receive data valid Receive error Receive data bit 3 Receive data bit 2 Receive data bit 1 Receive data bit 0 Receive clock KSZ8895MQ/RQ/FMQ MAC Mode Connection External PHY MTXEN MTXER MTXD3 MTXD2 MTXD1 MTXD0 MTXC MCOL MCRS MRXDV MRXER MRXD3 MRXD2 MRXD1 MRXD0 MRXC KSZ8895MQ/RQ/FMQ SW5-MII Signals SMRXDV Not used SMRXD[3] SMRXD[2] SMRXD[1] SMRXD[0] SMRXC SCOL SCRS SMTXEN SMTXER SMTXD[3] SMTXD[2] SMTXD[1] SMTXD[0] SMTXC Type Output Not used Output Output Output Output Input Input Input Input Input Input Input Input Input Input
Table 4. Switch MAC5 MII Signals
The switch MII interface operates in either MAC mode or PHY mode for KSZ8895MQ/RQ/FMQ. These interfaces are nibble-wide data interfaces and therefore run at one-quarter the network bit rate (not encoded). Additional signals on the transmit side indicate when data is valid or when an error occurs during transmission. Likewise, the receive side has indicators that convey when the data is valid and without physical layer errors. For half-duplex operation, there is a signal that indicates a collision has occurred during transmission. Note that the signal MRXER is not provided on the MII-SW interface for PHY mode operation and the signal MTXER is not provided on the SW-MII interface for MAC mode operation. Normally MRXER would indicate a receive error coming from the physical layer device. MTXER would indicate a transmit error from the MAC device. These signals are not appropriate for this configuration. For PHY mode operation with an external MAC, if the device interfacing with the KSZ8895MQ/RQ/FMQ has an MRXER pin, it should be tied low. For MAC mode operation with an external 38
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PHY, if the device interfacing with the KSZ8895MQ/RQ/FMQ has an MTXER pin, it should be tied low. Port 5 MAC 5 Switch SW5-RMII Interface for the KSZ8895RQ The Reduced Media Independent Interface (RMII) specifies a low pin count Media Independent Interface (MII). The KSZ8895RQ supports RMII interface at Port 5 switch side and provides a common interface at MAC5 layer in the device, and has the following key characteristics: * * Supports 10Mbps and 100Mbps data rates. Uses a single 50 MHz clock reference (provided internally or externally): in internal mode, the chip provides reference clock from SMRXC pin to SMTXC pin and provide the clock to the opposite clock input pin for RMII interface; in external mode, the chip receives 50MHz reference clock from an external oscillator or opposite RMII interface. Provides independent 2-bit wide (bi-bit) transmit and receive data paths.
*
KSZ8895RQ supports MAC5 RMII interfaces at the switch side: * * For the detail of SW5-RMII (Port 5 MAC5 RMII ) signals connection see the table below: The KSZ8895RQ can provide a 50MHz reference clock for both MAC to MAC and MAC to PHY RMII interfaces when SW5-RMII is used in the clock mode of the device (default with strap pin LED2_2 internal pull-up for the clock mode). The KSZ8895RQ also can receive 50MHz reference clock from external 50MHz clock source or opposite RMII to SW5-RMII SMTXC pin when the device is set to normal mode (the strap pin LED2_2 is pulled down).
*
When the device is strapped to normal mode by pin LED2_2 pull-down, the reference clock comes from SMTXC which will be as device's clock source. The external 25MHz crystal clock from pins X1/X2 will be ignored. Note: In the normal mode, the 50MHz clock from SMTXC will be as the clock source for whole device. The PHY5 PMTXC/PMREFCLK pin can not be used as the clock source for whole device, the pin of PMTXC/PMREFCLK can receive the 50MHz clock from PMRXC when device is strap to normal mode and external 50MHz reference clock comes in from pin SMTXC. In the normal mode, the 50MHz clock on pin SMRXC can be disabled by register, the PMRXC 50MHz clock can be used when P5-RMII interface is used also. There is a register 12 bit 6 to monitor the status of the device for the clock mode or normal mode. When use an external 50MHz clock source as RMII reference clock, the KSZ8895RQ should be set to normal mode by pull-down its LED2_2 strap-in pin first before power up reset or worm reset. The normal mode of KSZ8895RQ device will be start to work when get the 50MHz reference clock from pin SMTXC/SMREFCLK by an external 50MHz clock source. For the RMII connection examples, please refer to app note in the desigh kit.
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SW5-RMII MAC to MAC Connection (`PHY mode') External KSZ8895RQ KSZ8895RQ SW SW5-RMII Signal Type MAC
REF_CLK SMRXC Output (clock mode with 50MHz) (Normal mode without connection) Output Output Output Input Input Input
Description
SW5-RMII MAC to PHY Connection (`MAC mode') External KSZ8895RQ KSZ8895RQ SW PHY SW5-RMII Signal Type
-------SMTXC/SM REFCLK Input (clock comes from SMRXC in clock mode or external clock in normal mode) Input Input Input Output Output Output
Reference Clock
CRS_DV RXD1 RXD0 TX_EN TXD1 TXD0 (not used)
SMRXDV /SMCRSDV SMRXD[1] SMRXD[0] SMTXEN SMTXD[1] SMTXD[0] (not used) SMTXC/SM REFCLK
Carier sense/Receive data valid Receive data bit 1 Receive data bit 0 Transmit data enable Transmit data bit 1 Transmit data bit 0 Receive error
CRS_DV RXD1 RXD0 TX_EN TXD1 TXD0 (not used)
SMTXEN SMTXD[1] SMTXD[0] SMRXDV /SMCRSDV SMRXD[1] SMRXD[0] (not used)
---
Input (clock comes from SMRXC in clock mode or external clock in normal mode)
Reference Clock
REF_CLK
SMRXC
Output (clock mode with 50MHz ) (Normal mode without connection )
Note:
1.
MAC/PHY mode in RMII is difference with MAC/PHY mode in MII, there is no strap pin and register configuration request in RMII, just follow the signals connection in the table.
Table 5. Port 5 MAC5 SW5-RMII Connection
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SNI Interface Operation The serial network interface (SNI) is compatible with some controllers used for network layer protocol processing. This interface can be directly connected to these types of devices. The signals are divided into two groups, one for transmission and the other for reception. The signals involved are described in Table 5.
KSZ8895MQ/RQ/FMQ Signal SMTXEN SMTXD[0] SMTXC SCOL SMRXDV SMRXD[0] SMRXC
SNI Signal TXEN TXD TXC COL CRS RXD RXC
Description Transmit Enable Serial Transmit Data Transmit Clock Collision Detection Carrier Sense Serial Receive Data Receive Clock Table 6. SNI Signals
This interface is a bit-wide data interface and therefore runs at the network bit rate (not encoded). An additional signal on the transmit side indicates when data is valid. Likewise, the receive side has an indicator that conveys when the data is valid. For half-duplex operation there is a signal that indicates a collision has occurred during transmission.
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Advanced Functionality
QoS Priority Support The KSZ8895MQ/RQ/FMQ provides Quality of Service (QoS) for applications such as VoIP and video conferencing. The KSZ8895MQ/RQ/FMQ offer 1/2/4 priority queues option per port by setting the port registers control 16 bit1 and the port registers control 0 bit0, the 1/2/4 queues split as follows, [Port registers control 16 bit1, control 0 bit0]=00 single output queue as default. [Port registers control 16 bit1, control 0 bit0]=01 egress port can be split into two priority transmit queues. [Port registers control 16 bit1, control 0 bit0]=10 egress port can be split into four priority transmit queues. The four priority transmit queues is a new feature in the KSZ8895MQ/RQ/FMQ. The queue 3 is the highest priority queue and Queue 0 is the lowest priority queue. The port registers control 16 bit1 and the port registers control 0 bit0 are used to enable split transmit queues for ports 1, 2, 3, 4 and 5, respectively. If a port's transmit queue is not split, high priority and low priority packets have equal priority in the transmit queue. There is an additional option to either always deliver high priority packets first or use programmable weighted fair queuing for the four priority queues scale by the port registers control 10, 11, 12 and 13 (default value are 8, 4, 2, 1 by their bit[6:0]. Register 130 bit[7:6] Prio_2Q[1:0] is used when the 2 Queue configuration is selected, these bits are used to map the 2-bit result of IEEE 802.1p from the registers 128, 129 or TOS/DiffServ mapping from registers 144-159 (for 4 Queues) into two queues mode with priority high or low. Please see the descriptions of the register 130 bits [7:6] for detail. Port-Based Priority With port-based priority, each ingress port is individually classified as a priority 0-3 receiving port. All packets received at the priority 3 receiving port are marked as high priority and are sent to the high-priority transmit queue if the corresponding transmit queue is split. The Port Registers Control 0 Bits [4:3] is used to enable port-based priority for ports 1, 2, 3, 4 and 5, respectively. 802.1p-Based Priority For 802.1p-based priority, the KSZ8895MQ/RQ/FMQ examines the ingress (incoming) packets to determine whether they are tagged. If tagged, the 3-bit priority field in the VLAN tag is retrieved and compared against the "priority mapping" value, as specified by the registers 128 and 129, both register 128/129 can map 3-bit priority field of 0-7 value to 2-bit result of 0-3 priority levels. The "priority mapping" value is programmable. The following figure illustrates how the 802.1p priority field is embedded in the 802.1Q VLAN tag.
Bytes
8 Preamble
6 DA
6 SA
2 VPID
2 TCI
2 length LLC
46-1500 Data
4 FCS
Bits 802.1q VLAN Tag
16 Tagged Packet Type (8100 for Ethernet)
3 802.1p
1 CFI
12 VLAN ID
Figure 6. 802.1p Priority Field Format
802.1p-based priority is enabled by bit [5] of the port registers control 0 for ports 1, 2, 3, 4 and 5, respectively.
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The KSZ8895MQ/RQ/FMQ provides the option to insert or remove the priority tagged frame's header at each individual egress port. This header, consisting of the 2 bytes VLAN Protocol ID (VPID) and the 2-byte Tag Control Information field (TCI), is also referred to as the IEEE 802.1Q VLAN tag. Tag Insertion is enabled by bit [2] of the port registers control 0 and the port register control 8 to select which source port (ingress port) PVID can be inserted on the egress port for ports 1, 2, 3, 4 and 5, respectively. At the egress port, untagged packets are tagged with the ingress port's default tag. The default tags are programmed in the port registers control 3 and control 4 for ports 1, 2, 3, 4 and 5, respectively. The KSZ8895MQ/RQ/FMQ will not add tags to already tagged packets. Tag Removal is enabled by bit [1] of the port registers control 0 for ports 1, 2, 3, 4 and 5, respectively. At the egress port, tagged packets will have their 802.1Q VLAN Tags removed. The KSZ8895MQ/RQ/FMQ will not modify untagged packets. The CRC is recalculated for both tag insertion and tag removal. 802.1p Priority Field Re-mapping is a QoS feature that allows the KSZ8895MQ/RQ/FMQ to set the "User Priority Ceiling" at any ingress port by the port register control 2 bit 7. If the ingress packet's priority field has a higher priority value than the default tag's priority field of the ingress port, the packet's priority field is replaced with the default tag's priority field. DiffServ-Based Priority DiffServ-based priority uses the ToS registers (registers 144 to 159) in the Advanced Control Registers section. The ToS priority control registers implement a fully decoded, 128-bit Differentiated Services Code Point (DSCP) register to determine packet priority from the 6-bit ToS field in the IP header. When the most significant six bits of the ToS field are fully decoded, the resultant of the 64 possibilities of DSCP decoded is compared with the corresponding bits in the DSCP register to determine priority. Spanning Tree Support Port 5 is the designated port for spanning tree support. The other ports (Port 1 - Port 4) can be configured in one of the five spanning tree states via "transmit enable," "receive enable," and "learning disable" register settings in Registers 18, 34, 50, and 66 for Ports 1, 2, 3, and 4, respectively. The following description shows the port setting and software actions taken for each of the five spanning tree states. Disable state: the port should not forward or receive any packets. Learning is disabled. Port setting: "transmit enable = 0, receive enable = 0, learning disable = 1." Software action: the processor should not send any packets to the port. The switch may still send specific packets to the processor (packets that match some entries in the static table with "overriding bit" set) and the processor should discard those packets. Note: processor is connected to Port 5 via MII interface. Address learning is disabled on the port in this state. Blocking state: only packets to the processor are forwarded. Learning is disabled. Port setting: "transmit enable = 0, receive enable = 0, learning disable = 1" Software action: the processor should not send any packets to the port(s) in this state. The processor should program the "Static MAC table" with the entries that it needs to receive (e.g., BPDU packets). The "overriding" bit should also be set so that the switch will forward those specific packets to the processor. Address learning is disabled on the port in this state. Listening state: only packets to and from the processor are forwarded. Learning is disabled. Port setting: "transmit enable = 0, receive enable = 0, learning disable = 1. "Software action: The processor should program the static MAC table with the entries that it needs to receive (e.g. BPDU packets). The "overriding" bit should be set so that the switch will forward those specific packets to the processor. The processor may send packets to the port(s) in this state, see "Tail Tagging Mode" section for details. Address learning is disabled on the port in this state. Learning state: only packets to and from the processor are forwarded. Learning is enabled. Port setting: "transmit enable = 0, receive enable = 0, learning disable = 0." Software action: The processor should program the static MAC table with the entries that it needs to receive (e.g., January 2011 43
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BPDU packets). The "overriding" bit should be set so that the switch will forward those specific packets to the processor. The processor may send packets to the port(s) in this state, see "Tail Tagging Mode" section for details. Address learning is enabled on the port in this state. Forwarding state: packets are forwarded and received normally. Learning is enabled. Port setting: "transmit enable = 1, receive enable = 1, learning disable = 0." Software action: The processor should program the static MAC table with the entries that it needs to receive (e.g., BPDU packets). The "overriding" bit should be set so that the switch will forward those specific packets to the processor. The processor may send packets to the port(s) in this state, see "Tail Tagging Mode" section for details. Address learning is enabled on the port in this state. Rapid Spanning Tree Support There are three operational states of the Discarding, Learning, and Forwarding assigned to each port for RSTP: Discarding ports do not participate in the active topology and do not learn MAC addresses. Discarding state: the state includs three states of the disable, blocking and listening of STP. Port setting: "transmit enable = 0, receive enable = 0, learning disable = 1." Software action: the processor should not send any packets to the port. The switch may still send specific packets to the processor (packets that match some entries in the static table with "overriding bit" set) and the processor should discard those packets. When disable the port's learning capability (learning disable='1'), set the register 1 bit5 and bi4 will flush rapidly with the port related entries in the dynamic MAC table and static MAC table. Note: processor is connected to Port 5 via MII interface. Address learning is disabled on the port in this state. Ports in Learning states learn MAC addresses, but do not forward user traffic. Learning state: only packets to and from the processor are forwarded. Learning is enabled. Port setting: "transmit enable = 0, receive enable = 0, learning disable = 0." Software action: The processor should program the static MAC table with the entries that it needs to receive (e.g., BPDU packets). The "overriding" bit should be set so that the switch will forward those specific packets to the processor. The processor may send packets to the port(s) in this state, see "Tail Tagging Mode" section for details. Address learning is enabled on the port in this state. Ports in Forwarding states fully participate in both data forwarding and MAC learning. Forwarding state: packets are forwarded and received normally. Learning is enabled. Port setting: "transmit enable = 1, receive enable = 1, learning disable = 0." Software action: The processor should program the static MAC table with the entries that it needs to receive (e.g., BPDU packets). The "overriding" bit should be set so that the switch will forward those specific packets to the processor. The processor may send packets to the port(s) in this state, see "Tail Tagging Mode" section for details. Address learning is enabled on the port in this state. RSTP uses only one type of BPDU called RSTP BPDUs. They are similar to STP Configuration BPDUs with the exception of a type field set to "version 2" for RSTP and "version 0" for STP, and a flag field carrying additional information.
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Tail Tagging Mode The Tail Tag is only seen and used by the Port 5 interface, which should be connected to a processor by SW5-MII interface. The one byte tail tagging is used to indicate the source/destination port in Port 5. Only bit [3-0] are used for the destination in the tail tagging byte. Other bits are not used. The Tail Tag feature is enabled by setting register 12 bit 1.
Figure 7. Tail Tag Frame Format
Ingress to Port 5 (Host --> KSZ8895MQ/RQ/FMQ) Bit [3:0] 0,0,0,0 0,0,0,1 0,0,1,0 0,1,0,0 1,0,0,0 1,1,1,1 Bit [7:4] 0,0,0,0 0,0,0,1 0,0,1,0 0,0,1,1 x, 1,x,x 1, x,x,x Bit [1:0] 0,0 0,1 1,0 1,1 Queue 0 is used at destination port Queue 1 is used at destination port Queue 2 is used at destination port Queue 3 is used at destination port Whatever send packets to specified port in bit[3:0] Bit[6:0] will be ignored Source Port 1 (packets from Port 1) Port 2 (packets from Port 2) Port 3 (packets from Port 3) Port 4 (packets from Port 4) Table 7. Tail Tag Rules Destination Normal (Address Look up for destination) Port 1 (direct forward to Port1) Port 2 (direct forward to Port2) Port 3 (direct forward to Port3) Port 4 (direct forward to Port4) Port 1, 2,3 and 4 (direct forward to Port 1,2,3,4,)
Egress from Port 5 (KSZ8895MQ/RQ/FMQ --> Host)
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IGMP Support For Internet Group Management Protocol (IGMP) support in Layer 2, the KSZ8895MQ/RQ/FMQ provides two components: IGMP Snooping The KSZ8895MQ/RQ/FMQ traps IGMP packets and forwards them only to the processor (Port 5 SW5-MII). The IGMP packets are identified as IP packets (either Ethernet IP packets, or IEEE 802.3 SNAP IP packets) with IP version = 0x4 and protocol version number = 0x2. Multicast Address Insertion in the Static MAC Table Once the multicast address is programmed in the Static MAC Table, the multicast session is trimmed to the subscribed ports, instead of broadcasting to all ports. To enable IGMP support, set register 5 bit [6] to `1'. Also, "Tail tag mode" needs to be enabled, so that the processor knows which port the IGMP packet was received on. Enable "Tail tag mode" by setting Register 12 bit 0. Port Mirroring Support The KSZ8895MQ/RQ/FMQ supports "port mirror" comprehensively as: "Receive Only" mirror on a port All the packets received on the port will be mirrored on the sniffer port. For example, Port 1 is programmed to be "rx sniff," and Port 5 is programmed to be the "sniffer port." A packet, received on Port 1, is destined to Port 4 after the internal look-up. The KSZ8895MQ/RQ/FMQ will forward the packet to both Port 4 and Port 5. KSZ8895MQ/RQ/FMQ can optionally forward even "bad" received packets to Port 5. "Transmit Only" mirror on a port All the packets transmitted on the port will be mirrored on the sniffer port. For example, Port 1 is programmed to be "tx sniff," and Port 5 is programmed to be the "sniffer port." A packet, received on any of the ports, is destined to Port 1 after the internal look-up. The KSZ8895MQ/RQ/FMQ will forward the packet to both Ports 1 and 5. "Receive and Transmit" mirror on two ports. All the packets received on port A AND transmitted on port B will be mirrored on the sniffer port. To turn on the "AND" feature, set Register 5 bit 0 to 1. For example, Port 1 is programmed to be "rx sniff," Port 2 is programmed to be "transmit sniff," and Port 5 is programmed to be the "sniffer port." A packet, received on Port 1, is destined to Port 4 after the internal look-up. The KSZ8895MQ/RQ/FMQ will forward the packet to Port 4 only, since it does not meet the "AND" condition. A packet, received on Port 1, is destined to Port 2 after the internal look-up. The KSZ8895MQ/RQ/FMQ will forward the packet to both Port 2 and Port 5. Multiple ports can be selected to be "rx sniffed" or "tx sniffed." And any port can be selected to be the "sniffer port." All these per port features can be selected through Register 17. VLAN Support The KSZ8895MQ/RQ/FMQ supports 128 active VLANs and 4096 possible VIDs specified in IEEE 802.1q. KSZ8895MQ/RQ/FMQ provides a 128-entry VLAN table, which correspond to 4096 possible VIDs and converts to FID (7 bits) for address look-up max 128 active VLANs. If a non-tagged or null-VID-tagged packet is received, then the ingress port VID is used for look-up when 802.1q is enabled by the global register 5 control 3 bit 7. In the VLAN mode, the look-up process starts from VLAN table look-up to determine whether the VID is valid. If the VID is not valid, the packet will then be dropped and its address will not be learned. If the VID is valid, FID is retrieved for further look-up by the static MAC table or dynamic MAC table. FID+DA is used to determine the destination port. The followed table describles the difference actions at different situstions of DA and FID+DA in the static MAC table and dynamic MAC table after the VLAN table finish a look-up action. FID+SA is used for learning purposes. The followed table also describles how to learning in the dynamic MAC table when VLAN table has done a look-up and the static MAC table without a valid entry.
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DA found in Static MAC table No No Yes Yes Yes Yes
USE FID Flag? Don't care Don't care 0 1 1 1
FID Match? Don't care Don't care Don't care No No Yes
DA+FID found in Dynamic MAC table No Yes Don't care No Yes Don't care
Action Broadcast to the membership ports defined in the VLAN table bit [11:7]. Send to the destination port defined in the dynamic MAC table bit [57:55]. Send to the destination port(s) defined in the static MAC table bit [52:48]. Broadcast to the membership ports defined in the VLAN table bit [11:7]. Send to the destination port defined in the dynamic MAC table bit [57:55]. Send to the destination port(s) defined in the static MAC table bit [52:48].
Table 8. FID+DA Look-Up in the VLAN Mode
SA+FID found in Dynamic MAC table No Yes
Action The SA+FID will be learned into the dynamic table. Time stamp will be updated. Table 9. FID+SA Look-Up in the VLAN Mode
Advanced VLAN features are also supported in KSZ8895MQ/RQ/FMQ, such as "VLAN ingress filtering" and "discard non PVID" defined in bits [6:5] of the port Register Control 2. These features can be controlled on a port basis. Rate Limiting Support The KSZ8895MQ/RQ/FMQ provides a fine resolution hardware rate limiting. The rate step is 64Kbps when the rate limit is less than 1Mbps rate for 100BT or 10BT. The rate step is 1Mbps when the rate limit is more than 1Mbps rate for 100BT or 10BT (refer to Data Rate Selection Table which follow the end of the Port Register Queue 0-3 Ingress/Egress Limit Control section). The rate limit is independently on the "receive side" and on the "transmit side" on a per port basis. For 10BASE-T, a rate setting above 10 Mbps means the rate is not limited. On the receive side, the data receive rate for each priority at each port can be limited by setting up Ingress Rate Control Registers. On the transmit side, the data transmit rate for each priority queue at each port can be limited by setting up Egress Rate Control Registers. The size of each frame has options to include minimum IFG (Inter Frame Gap) or Preamble byte, in addition to the data field (from packet DA to FCS). Ingress Rate Limit For ingress rate limiting, KSZ8895MQ/RQ/FMQ provides options to selectively choose frames from all types, multicast, broadcast, and flooded unicast frames by bits [3-2] of the port rate limit control register. The KSZ8895MQ/RQ/FMQ counts the data rate from those selected type of frames. Packets are dropped at the ingress port when the data rate exceeds the specified rate limit or the flow control takes effect without packet dropped when the ingress rate limit flow control is enabled by the port rate limit control register bit 4. The ingress rate limiting supports the port-based, 802.1p and DiffServ-based priorities, the port-based priority is fixed priority 0-3 selection by bits [4-3] of the port register control 0. The 802.1p and DiffServ-based priority can be mapped to priority 0-3 by default of the register 128 and 129. In the ingress rate limit, set register 135 global control 19 bit3 for queue-based rate limit to be enabled if use two queues or four queues mode, all related ingress ports and egress port should be spitted to two queues or four queues mode by the port registers control 9 and control 0. The four queues mode will use Q0-Q3 for priority 0-3 by bit [6-0] of the port register ingress limit control 1-4. The two queues mode will use Q0Q1 for priority 0-1by bit [6-0] of the port register ingress limit control 1-2. The priority levels in the packets of the 802.1p and DiffServ can be programmed to priority 0-3 by the register 128 and 129 for a re-mapping.
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KSZ8895MQ/RQ/FMQ
Egress Rate Limit For egress rate limiting, the Leaky Bucket algorithm is applied to each output priority queue for shaping output traffic. Inter frame gap is stretched on a per frame base to generate smooth, non-burst egress traffic. The throughput of each output priority queue is limited by the egress rate specified by the data rate selection table followed the egress rate limit control registers. If any egress queue receives more traffic than the specified egress rate throughput, packets may be accumulated in the output queue and packet memory. After the memory of the queue or the port is used up, packet dropping or flow control will be triggered. As a result of congestion, the actual egress rate may be dominated by flow control/dropping at the ingress end, and may be therefore slightly less than the specified egress rate. The egress rate limiting supports the port-based, 802.1p and DiffServ-based priorities, the port-based priority is fixed priority 0-3 selection by bits [4-3] of the port register control 0. The 802.1p and DiffServ-based priority can be mapped to priority 0-3 by default of the register 128 and 129. In the egress rate limit, set register 135 global control 19 bit3 for queue-based rate limit to be enabled if use two queues or four queues mode, all related ingress ports and egress port should be spitted to two queues or four queues mode by the port registers control 9 and control 0. The four queues mode will use Q0-Q3 for priority 0-3 by bit [6-0] of the port register egress limit control 1-4. The two queues mode will use Q0Q1 for priority 0-1by bit [6-0] of the port register egress limit control 1-2. The priority levels in the packets of the 802.1p and DiffServ can be programmed to priority 0-3 by the register 128 and 129 for a re-mapping. When egress rate limited just use one queue per port for the egress port rate limit. The priority packets will be based up on the data rate selection table with the rate limit exact number. If egress rate limit use more than one queue per port for the egress port rate limit, then the highest priority packets will be based up on the data rate selection table for the rate limit exact number. Other lower priority packet rates will be limited based up on 8:4:2:1 (default) priority ratio which is based on the highest priority rate. The transmit queue priority ratio is programmable. To reduce congestion, it is a good practice to make sure the egress bandwidth exceeds the ingress bandwidth. Transmit Queue Ratio Programming In transmit queues 0-3 of the egress port, the default priority ratio is 8:4:2:1, the priority ratio can be programmed by the port registers control 10, 11, 12 and 13. When the transmit rate exceed the ratio limit in the transmit queue, the transmit rate will be limited by the transmit queue 0-3 ratio of the port register control 10, 11, 12 and 13. The highest priority queue will be no limited, other lower priority queues will be limited based on the transmit queue ratio. Filtering for Self-Address, Unknown Unicast/Multicast Address and Unknown VID Packet/IP Multicast Enable Self-address filtering, the unknown unicast packet filtering and forwarding by the Register 131 Global Control 15. Enable Unknown multicast packet filtering and forwarding by the Register 132 Global Control 16. Enable Unknown VID packet filtering and forwarding by the Register 133 Global Control 17. Enable Unknown IP multicast packet filtering and forwarding by the Register 134 Global Control 18. This function is very useful in preventing those kinds of packets that could degrade the quality of the port in applications such as voice over Internet Protocol (VoIP) and the daisy chain connection to prevent packets into endless loop. Configuration Interface I C Master Serial Bus Configuration If a 2-wire EEPROM exists, then the KSZ8895MQ/RQ/FMQ can perform more advanced features like broadcast storm protection and rate control. The EEPROM should have the entire valid configuration data from Register 0 to Register 255 defined in the "Memory Map," except the chipID=0 in the register1 and the status registers. After reset, the KSZ8895MQ/RQ/FMQ will start to read all 255 registers sequentially from the EEPROM. The configuration access time (tprgm) is less than 30ms, as shown in Figure 12.
2
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RST_N SCL SDA
.... .... ....
t prgm <30 ms
Figure 8. KSZ8895MQ/RQ/FMQ EEPROM Configuration Timing Diagram
To configure the KSZ8895MQ/RQ/FMQ with a pre-configured EEPROM use the following steps: 1. At the board level, connect pin 110 on the KSZ8895MQ/RQ/FMQ to the SCL pin on the EEPROM. Connect pin 111 on the KSZ8895MQ/RQ/FMQ to the SDA pin on the EEPROM. 2. Set the input signals PS[1:0] (pins 113 and 114, respectively) to "00." This puts the KSZ8895MQ/RQ/FMQ serial 2 bus configuration into I C master mode. 3. Be sure the board-level reset signal is connected to the KSZ8895MQ/RQ/FMQ reset signal on pin 115 (RST_N). 4. Program the contents of the EEPROM before placing it on the board with the desired configuration data. Note that the first byte in the EEPROM must be "95" for the loading to occur properly. If this value is not correct, all other data will be ignored. 5. Place EEPROM on the board and power up the board. Assert the active-low board level reset to RST_N on the KSZ8895MQ/RQ/FMQ. After the reset is de-asserted, the KSZ8895MQ/RQ/FMQ will begin reading configuration data from the EEPROM. The configuration access time (tprgm) is less than 30ms. Note: For proper operation, make sure that pin 47 (PWRDN_N) is not asserted during the reset operation. SPI Slave Serial Bus Configuration The KSZ8895MQ/RQ/FMQ can also act as a SPI slave device. Through the SPI, the entire feature set can be enabled, including "VLAN," "IGMP snooping," "MIB counters," etc. The external master device can access any register from Register 0 to Register 127 randomly. The system should configure all the desired settings before enabling the switch in the KSZ8895MQ/RQ/FMQ. To enable the switch, write a "1" to Register 1 bit 0. Two standard SPI commands are supported (00000011 for "READ DATA," and 00000010 for "WRITE DATA"). To speed configuration time, the KSZ8895MQ/RQ/FMQ also supports multiple reads or writes. After a byte is written to or read from the KSZ8895MQ/RQ/FMQ, the internal address counter automatically increments if the SPI Slave Select Signal (SPIS_N) continues to be driven low. If SPIS_N is kept low after the first byte is read, the next byte at the next address will be shifted out on SPIQ. If SPIS_N is kept low after the first byte is written, bits on the Master Out Slave Input (SPID) line will be written to the next address. Asserting SPIS_N high terminates a read or write operation. This means that the SPIS_N signal must be asserted high and then low again before issuing another command and address. The address counter wraps back to zero once it reaches the highest address. Therefore the entire register set can be written to or read from by issuing a single command and address. The default SPI clock speed is 12.5MHz. The KSZ8895MQ/RQ/FMQ is able to support a SPI bus up to 25MHz (set register 12 bit [5:4]=0x10). A high performance SPI master is recommended to prevent internal counter overflow.
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Micrel, Inc. To use the KSZ8895MQ/RQ/FMQ SPI: 1. At the board level, connect KSZ8895MQ/RQ/FMQ pins as follows:
KSZ8895MQ/RQ/FMQ Pin Number 112 110 111 109 KSZ8895MQ/RQ/FMQ Signal Name SPIS_N SPIC SPID SPIQ Microprocessor Signal Description SPI Slave Select SPI Clock Master Out Slave Input Master In Slave Output Table 10. SPI Connections
KSZ8895MQ/RQ/FMQ
2. Set the input signals PS[1:0] (pins 113 and 114, respectively) to "10" to set the serial configuration to SPI slave mode. 3. Power up the board and assert a reset signal. After reset wait 100s, the start switch bit in Register 1 will be set to `0'. Configure the desired settings in the KSZ8895MQ/RQ/FMQ before setting the start register to `1.' 4. Write configuration to registers using a typical SPI write data cycle as shown in Figure 9 or SPI multiple write as shown in Figure 11. Note that data input on SPID is registered on the rising edge of SPIC. 5. Registers can be read and configuration can be verified with a typical SPI read data cycle as shown in Figure 10 or a multiple read as shown in Figure 12. Note that read data is registered out of SPIQ on the falling edge of SPIC. 6. After configuration is written and verified, write a `1' to Register 1 bit 0 to begin KSZ8895MQ/RQ/FMQ switch operation.
SPIS_N SPIC SPID SPIQ X 0 0 0 0 0 0 1 0 A7 A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
WRITE COMMAND
WRITE ADDRESS
WRITE DATA
Figure 9. SPI Write Data Cycle
SPIS_N SPIC SPID SPIQ X 0 0 0 0 0 0 1 1 A7 A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
READ COMMAND
READ ADDRESS
READ DATA
Figure 10. SPI Read Data Cycle
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SPIS_N SPIC SPID SPIQ X 0 0 0 0 0 0 1 0 A7 A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
WRITE COMMAND SPIS_N SPIC SPID SPIQ
D7 D6 D5 D4 D4 D2 D1 D0 D7 D6 D5
WRITE ADDRESS
Byte 1
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Byte 2
Byte 3 ...
Byte N
Figure 11. SPI Multiple Write
SPIS_N SPIC SPID SPIQ X 0 0 0 0 0 0 1 1 A7 A6 A5 A4 A3 A2 A1 A0 X
D7
X
D6
X
D5
X
D4
X
D3
X
D2
X
D1
X
D0
READ COMMAND SPIS_N SPIC SPID SPIQ X
D7
READ ADDRESS
Byte 1
X
D6
X
D5
X
D4
X
D3
X
D2
X
D1
X
D0
X
D7
X
D6
X
D5
X
D4
X
D3
X
D2
X
D1
X
D0
X
D7
X
D6
X
D5
X
D4
X
D3
X
D2
X
D1
X
D0
Byte 2
Byte 3 ...
Byte N
Figure 12. SPI Multiple Read
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MII Management Interface (MIIM) The KSZ8895MQ/RQ/FMQ supports the standard IEEE 802.3 MII Management Interface, also known as the Management Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the states of the KSZ8895MQ/RQ/FMQ. An external device with MDC/MDIO capability is used to read the PHY status or configure the PHY settings. Further details on the MIIM interface are found in Clause 22.2.4.5 of the IEEE 802.3u Specification. The MIIM interface consists of the following: A physical connection that incorporates the data line (pin 108 MDIO) and the clock line (pin 107 MDC). A specific protocol that operates across the aforementioned physical connection that allows an external controller to communicate with the KSZ8895MQ/RQ/FMQ device. Access to a set of eight 16-bit registers, consisting of 8 standard MIIM registers [0:5h], 1d and 1f MIIM registers per port. The MIIM Interface can operate up to a maximum clock speed of 10MHz MDC clock. The following table depicts the MII Management Interface frame format.
Preamble Start of Frame 01 01 Read/Write OP Code 10 01 PHY Address Bits [4:0] AAAAA AAAAA REG Address Bits [4:0] RRRRR RRRRR TA Data Bits [15:0] Idle
Read Write
32 1's 32 1's
Z0 10
DDDDDDDD_DDDDDDDD DDDDDDDD_DDDDDDDD
Z Z
Table 11. MII Management Interface Frame Format
The MIIM interface does not have access to all the configuration registers in the KSZ8895MQ/RQ/FMQ. It can only access the standard MIIM registers. See "MIIM Registers". The SPI interface and MDC/MDIO SMI mode, on the other hand, can be used to access all registers with the entire KSZ8895MQ/RQ/FMQ feature set. Serial Management Interface (SMI) The SMI is the KSZ8895MQ/RQ/FMQ non-standard MIIM interface that provides access to all KSZ8895MQ/RQ/FMQ configuration registers. This interface allows an external device with MDC/MDIO interface to completely monitor and control the states of the KSZ8895MQ/RQ/FMQ. The SMI interface consists of the following: A physical connection that incorporates the data line (MDIO) and the clock line (MDC). A specific protocol that operates across the aforementioned physical connection that allows an external controller to communicate with the KSZ8895MQ/RQ/FMQ device. Access all KSZ8895MQ/RQ/FMQ configuration registers. Register access includes the Global, Port and Advanced Control Registers 0-255 (0x00 - 0xFF), and indirect access to the standard MIIM registers [0:5] and custom MIIM registers [29, 31]. The SMI Interface can operate up to a maximum clock speed of 10MHz MDC clock. The following table depicts the SMI frame format.
Preamble Start of Frame Read/Write OP Code 10 01 PHY Address Bits [4:0] Read Write 32 1's 32 1's 01 01 RR11R RR11R REG Address Bits [4:0] RRRRR RRRRR Z0 10 0000_0000_DDDD_DDDD xxxx_xxxx_DDDD_DDDD Z Z TA Data Bits [15:0] Idle
Table 12. Serial Management Interface (SMI) Frame Format
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SMI register Read access is selected when OP Code is set to "10" and bits [2:1] of the PHY address is set to `11'. SMI register Write access is selected when OP Code is set to "01" and bits [2:1] of the PHY address is set to `11'. The 8-bit register address is the concatenation of {PHY address bits [4:3], PHY address bits [0], REG address bit[4:0]}. Since the switch configuration registers are 8-bit wide, only the lower 8 bits of Data Bits [15:0] are used. To access the KSZ8895MQ/RQ/FMQ registers 0-255 (0x00 - 0xFF), the following applies: PHYAD [4,3,0] and REGAD [4:0] are concatenated to form the 8-bit address; that is, {PHYAD[4,3,0], REGAD[4:0]} = bits [7:0] of the 8-bit address. Registers are 8 data bits wide. For read operation, data bits [15:8] are read back as 0's. For write operation, data bits [15:8] are not defined, and hence can be set to either 0's or 1's. SMI register access is the same as the MIIM register access, except for the register access requirements presented in this section.
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Register Description
Offset Decimal 0-1 2-13 14-15 16-20 21-23 24-31 32-36 37-39 40-47 48-52 53-55 56-63 64-68 69-71 72-79 80-84 85-87 88-95 96-103 104-109 110-111 112-120 121-123 124-125 126-127 128-135 136 137-143 144-145 146-159 160-175 176-190 191 Hex 0x00-0x01 0x02-0x0D 0x0E-0x0F 0x10-0x14 0x15-0x17 0x18-0x1F 0x20-0x24 0x25-0x27 0x28-0x2F 0x30-0x34 0x35-0x37 0x38-0x3F 0x40-0x44 0x45-0x47 0x48-0x4F 0x50-0x54 0x55-0x57 0x58-0x5F 0x60-0x67 0x68-0x6D 0x6E-0x6F 0x70-0x78 0x79-0x7B 0x7C-0x7D 0x7E-0x7F 0x80-0x87 0x88 0x89-0x8F 0x90-0x91 0x92-0x9F 0xA0-0xAF 0xB0-0xBE 0xBF Description Chip ID Registers. Global Control Registers. Power Down Management Control Registers. Port 1 Control Registers. Port 1 Reserved (Factory Test Registers). Port 1 Control/Status Registers. Port 2 Control Registers. Port 2 Reserved (Factory Test Registers). Port 2 Control/Status Registers. Port 3 Control Registers. Port 3 Reserved (Factory Test Registers). Port 3 Control/Status Registers. Port 4 Control Registers. Port 4 Reserved (Factory Test Registers). Port 4 Control/Status Registers. Port 5 Control Registers. Port 5 Reserved (Factory Test Registers). Port 5 Control/Status Registers. Reserved (Factory Testing Registers). MAC Address Registers. Indirect Access Control Registers. Indirect Data Registers. Reserved (Factory Testing Registers). Port Interrupt Registers. Reserved (Factory Testing Registers). Global Control Registers. Switch Self Test Control Register. QM Global Control Registers. TOS Priority Control Registers. TOS Priority Control Registers. Reserved (Factory Testing Registers). Port 1 Control Registers. Reserved (Factory Testing Register): Transmit Queue Remap Base Register.
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Offset Decimal 192-206 207 208-222 223 224-238 239 240-254 255 Hex 0xC0-0xCE 0xCF 0xD0-0xDE 0xDF 0xE0-0xEE 0xEF 0xF0-0xFE 0xFF Description Port 2 Control Registers. Reserved (Factory Testing Register). Port 3 Control Registers. Reserved (Factory Testing Register). Port 4 Control Registers. Reserved (Factory Testing Register). Port 5 Control Registers. Reserved (Factory Testing Register).
KSZ8895MQ/RQ/FMQ
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Global Registers
Address Name Description Mode Default
Register 0 (0x00): Chip ID0
7-0 Family ID Chip family. RO 0x95
Register 1 (0x01): Chip ID1 / Start Switch
7-4 Chip ID 0100 = KSZ8895MQ 0101 = KSZ8895TMQ 0110 = KSZ8995RQ ...... Revision ID 1, start the chip when external pins (PS1, PS0) = (1,0) Note: in (PS1,PS0) = (0,0) mode, the chip will start automatically, after trying to read the external EEPROM. If EEPROM does not exist, the chip will use default values for all internal registers. If EEPROM is present, the contents in the EEPROM will be checked. The switch will check: 7 Register 0 = 0x95, (2) Register 1 [7:4] = Availible chip ID. If this check is OK, the contents in the EEPROM will override chip register default values =0, chip will not start when external pins (PS1, PS0) = (1,0) or (0,1). Note: (PS1, PS0) = (1,1) for Factory test only. 0, stop the switch function of the chip. RO 0x4 is MQ 0x5 is TMQ 0x6 is RQ ...... 0x0 0
3-1 0
Revision ID Start Switch
RO R/W
Register 2 (0x02): Global Control 0
7 6 5 New Back-off Enable Reserved Flush dynamic MAC table New Back-off algorithm designed for UNH 1 = Enable 0 = Disable Reserved. Flush the entire dynamic MAC table for RSTP 1 = Trigger the flush dynamic MAC table operation. This bit is self clear 0 = normal operation Note: All the entries associated with a port that has its learning capability being turned off (Learning Disable) will be flushed. If you want to flush the entire Table, all ports learning capability must be turned off. Flush the matched entries in static MAC table for RSTP 1 = Trigger the flush static MAC table operation. This bit is self clear 0 = normal operation Note: The matched entry is defined as the entry whose Forwarding Ports field contains a single port and MAC address with unicast. This port, in turn, has its learning capability being turned off (Learning Disable). Per port, multiple entries can be qualified as matched entries. R/W RO R/W (SC) 0 0 0
4
Flush static MAC table
R/W (SC)
0
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Address 3 Name Enable PHY MII/RMII Description 1, enable PHY P5-MII/RMII interface (default). Note: if not enabled, the switch will tri-state all outputs.
KSZ8895MQ/RQ/FMQ
Mode R/W Default 1 Pin LED[5][1] strap option. PD(0): isolate. PU(1): Enable. Note: LED[5][1] has internal pullup (PU). 1 0
2 1
Reserved UNH Mode
N/A Don't change. 1, the switch will drop packets with 0x8808 in T/L filed, or DA=01-80-C2-00-00-01. 0, the switch will drop packets qualified as "flow control" packets. 1, link change from "link" to "no link" will cause fast aging (<800s) to age address table faster. After an age cycle is complete, the age logic will return to normal (300 +/- 75 seconds ). Note: If any port is unplugged, all addresses will be automatically aged out.
RO R/W
0
Link Change Age
R/W
0
Register 3 (0x03): Global Control 1
7 6 5 Pass All Frames 2K Byte packet support IEEE 802.3x Transmit Flow Control Disable 1, switch all packets including bad ones. Used solely for debugging purpose. Works in conjunction with sniffer mode. 1 = enable support 2K Byte packet 0 = disable support 2K Byte packet 0, will enable transmit flow control based on AN result. 1, will not enable transmit flow control regardless of AN result. R/W R/W R/W 0 0 0 Pin PMRXD3 strap option. PD(0): Enable Tx flow control (default). PU(1): Disable Tx/Rx flow control. Note: PMRXD3 has internal pulldown. 0 Pin PMRXD3 strap option. PD (0): Enable Rx flow control (default). PU(1): Disable Tx/Rx flow control. Note: PMRXD3 has internal pulldown. 0
4
IEEE 802.3x Receive Flow Control Disable
0, will enable receive flow control based on AN result. 1, will not enable receive flow control regardless of AN result. Note: Bit 5 and bit 4 default values are controlled by the same pin, but they can be programmed independently.
R/W
3
Frame Length Field Check
1, will check frame length field in the IEEE packets If the actual length does not match, the packet will be dropped (for L/T <1500) .
R/W
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Address 2 Name Aging Enable Description 1, Enable age function in the chip. 0, Disable aging function.
KSZ8895MQ/RQ/FMQ
Mode R/W Default 1 Pin LED[5][2] strap option. PD(0): Aging disable. PU(1): Aging enable (default). Note: LED[5][2] has internal pull up. 0 0 Pin PMRXD0 strap option. PD(0): Disable aggressive back off (default). PU(1): Aggressive back off. Note: PMRXD0 has internal pull down.
1 0
Fast age Enable Aggressive Back Off Enable
1 = Turn on fast age (800s). 1 = Enable more aggressive back-off algorithm in half duplex mode to enhance performance. This is not an IEEE standard.
R/W R/W
Register 4 (0x04): Global Control 2
7 Unicast Port-VLAN Mismatch Discard This feature is used for port VLAN (described in Register 17, Register 33...). 1, all packets can not cross VLAN boundary. 0, unicast packets (excluding unknown/ multicast/broadcast) can cross VLAN boundary. 1, "Broadcast Storm Protection" does not include multicast packets. Only DA=FFFFFFFFFFFF packets will be regulated. 0, "Broadcast Storm Protection" includes DA = FFFFFFFFFFFF and DA[40] = 1 packet. 1, carrier sense based backpressure is selected. 0, collision based backpressure is selected. 1, fair mode is selected. In this mode, if a flow control port and a non-flow control port talk to the same destination port, then packets from the non-flow control port may be dropped. This is to prevent the flow control port from being flow controlled for an extended period of time. 0, in this mode, if a flow control port and a non-flow control port talk to the same destination port, the flow control port will be flow controlled. This may not be "fair" to the flow control port. R/W 1
6
Multicast Storm Protection Disable
R/W
1
5 4
Back Pressure Mode Flow Control and Back Pressure fair Mode
R/W R/W
1 1
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Address 3 Name No Excessive Collision Drop Description 1, the switch will not drop packets when 16 or more collisions occur. 0, the switch will drop packets when 16 or more collisions occur.
KSZ8895MQ/RQ/FMQ
Mode R/W Default 0 Pin PMRXD1 strap option. PD(0): (default ) Drop excessive collision packets. PU(1): Don't drop excessive collision packets. Note: PMRXD1 has internal pull down. 0
2
Huge Packet Support
1, will accept packet sizes up to 1916 bytes (inclusive). This bit setting will override setting from bit 1 of the same register. 0, the max packet size will be determined by bit 1 of this register. 1, will accept packet sizes up to 1536 bytes (inclusive). 0, 1522 bytes for tagged packets (not including packets with STPID from CPU to ports 1-4), 1518 bytes for untagged packets. Any packets larger than the specified value will be dropped.
R/W
1
Legal Maximum Packet Size Check Disable
R/W
0
Reserved
N/A
RO
0 Pin PMRXER strap option. PD(0): (default) 1518/1522 byte packets. PU(1): 1536 byte packets. Note: PMRXER has internal pulldown. 0
Register 5 (0x05): Global Control 3
7 6 5 802.1q VLAN Enable IGMP Snoop Enable on Switch SW5-MII/RMII Interface Enable Direct Mode on Switch SW5-MII/RMII Interface Enable Pre-Tag on Switch SW5-MII/TMI/RMIII Interface Reserved Enable "Tag" Mask 1, 802.1q VLAN mode is turned on. VLAN table needs to set up before the operation. 0, 802.1q VLAN is disabled. 1, IGMP snoop enabled. All the IGMP packets will be forwarded to Switch MII/RMII port. 0, IGMP snoop disabled. 1, direct mode on Port 5. This is a special mode for the Switch MII/RMII interface. Using preamble before MRXDV to direct switch to forward packets, bypassing internal look-up. 0, normal operation. 1, packets forwarded to Switch MII/RMII interface will be pre-tagged with the source port number (preamble before MRXDV). 0, normal operation. N/A 1, the last 5 digits in the VID field are used as a mask to determine which port(s) the packet should be forwarded to. 0, no tag masks. Note: you need to turn off the 802.1q VLAN mode (reg0x5, bit 7 = 0) for this bit to work. R/W R/W R/W 0 0 0
4
R/W
0
3-2 1
RO R/W
00 0
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Address 0 Name Sniff Mode Select Description 1, will do Rx AND Tx sniff (both source port and destination port need to match). 0, will do Rx OR Tx sniff (Either source port or destination port needs to match). This is the mode used to implement Rx only sniff.
KSZ8895MQ/RQ/FMQ
Mode R/W Default 0
Register 6 (0x07): Global Control 4
7 Switch SW5-MII/RMII Back Pressure Enable Switch SW5-MII/RMII Half-Duplex Mode 1, enable half-duplex back pressure on switch MII/RMII interface. 0, disable back pressure on switch MII interface. 1, enable MII/RMII interface half-duplex mode. 0, enable MII/RMII interface full-duplex mode. R/W 0
6
R/W
5
Switch SW5-MII/RMII Flow Control Enable
1, enable full-duplex flow control on switch MII/RMII interface. 0, disable full-duplex flow control on switch MII/RMII interface.
R/W
4
Switch SW5-MII/RMII Speed
1, the switch SW5-MII/RMII is in 10Mbps mode. 0, the switch SW5-MII/RMII is in 100Mbps mode.
R/W
3 2-0
Null VID Replacement Broadcast Storm Protection Rate Bit [10:8]
1, will replace null VID with port VID (12 bits). 0, no replacement for null VID. This along with the next register determines how many "64 byte blocks" of packet data allowed on an input port in a preset period. The period is 50ms for 100BT or 500ms for 10BT. The default is 1%.
R/W R/W
0 Pin SMRXD2 strap option. PD(0): (default) Full-duplex mode. PU(1): Halfduplex mode. Note: SMRXD2 has internal pulldown. 0 Pin SMRXD3 strap option. PD(0): (default) Disable flow control. PU(1): enable flow control. Note: SMRXD3 has internal pulldown. 0 Pin SMRXD1 strap option. PD(0): (default) Enable 100Mbps. PU(1): Enable 10Mbps. Note: SMRXD1 has internal pulldown. 0 000
Register 7 (0x07): Global Control 5
7-0 Broadcast Storm Protection Rate Bit [7:0] This along with the previous register determines how many "64 byte blocks" of packet data are allowed on an input port in a preset period. The period is 50ms for 100BT or 500ms for 10BT. The default is 1%. R/W 0x4A
(1)
Register 8 (0x08): Global Control 6
7-0 Factory Testing N/A Don't change. RO 0x00
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Address Name Description
KSZ8895MQ/RQ/FMQ
Mode Default
Register 9 (0x09): Global Control 7
7-0
Note:
Factory Testing
N/A Don't change.
RO
0x4C
7 148,800 frames/sec x 50ms/interval x 1% = 74 frames/interval (approx.) = 0x4A.
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Address
Name
Description
Mode
Default
Register 10 (0x0A): Global Control 8
7-0 Factory Testing N/A Don't change. RO 0x00
Register 11 (0x0B): Global Control 9
7 6 Reversed Port 5 SW5- RMII reference clock edge select N/A Don't change. RQ: Select the data sampling edge of Switch MAC5 SW5- RMII reference clock: 1 = data sampling on negative edge of refclk 0 = data sampling on positive edge of refclk (default) Note:MQ/FMQ is reserved with read only for this bit. 5 4 3 2 1 Reserved Reserved PHY Power Save Reserved LED Mode N/A Don't change. N/A Don't change. 1 = disable PHY power save mode. 0 = enable PHY power save mode. N/A Don't change. 0 = led mode 0. 1 = led mode 1. Mode 0, link at 100/Full LEDx[2,1,0]=0,0,0 LEDx[2,1,0]=0,1,0 10/Full LEDx[2,1,0]=0,0,1 LEDx[2,1,0]=0,1,1 Mode 1, link at 100/Full LEDx[2,1,0]=0,1,0 LEDx[2,1,0]=0,1,1 10/Full LEDx[2,1,0]=1,0,0 LEDx[2,1,0]=1,0,1 (0=LED on, 1=LED off) Mode 0 LEDX_2 LEDX_1 LEDX_0 0 SPI/SMI read sampling clock edge select Lnk/Act Fulld/Col Speed 100/Half 10/Half 100/Half 10/Half RO RO R/W RO R/W 0 0 0 0 0 Pin SMRXD0 - strap option. Pulldown(0): Enabled led mode 0. Pullup(1): Enabled led mode 1. Note: SMRXD0 has internal pulldown 0. RO R/W 0 0
Mode 1 100Lnk/Act 10Lnk/Act Fulld R/W 0
Select the SPI/SMI clock edge for sampling SPI/SMI read data. 1 = trigger by rising edge of SPI/SMI clock (for high speed SPI about 25MHz and SMI about 10MHz) 0 = trigger by falling edge of SPI/SMI clock.
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Address Name Description
KSZ8895MQ/RQ/FMQ
Mode Default
Register 12 (0x0C): Global Control 10
7 6 Reserved Satus of device with RMII interface at clock mode or normal mode, default is clock mode with 25MHz Crystal clock from pins X1/X2 (used for RMII of the KSZ8895RQ only) Reserved 1 = The device is in clock mode when use RMII interface, 25 MHz Crystal clock input as clock source for internal PLL. This internal PLL will provide the 50 MHz output on the pin SMRXC for RMII reference clock (Default). 0 = The device is in normal mode when use SW4-RMII interface and 50 MHz clock input from external clock through pin SM4TXC as device's clock source and internal PLL clock source from this pin not from the 25MHz crystal. Note: This bit is set by strap option only. Write to this bit has no effect on mode selection. Note: The normal mode is used in SW5-RMII interface reference clock from external. 5-4 CPU interface clock select Select the internal clock speed for SPI, MDI interface: 00 = 41.67MHz (SPI up to 6.25MHz, MDC up to 6MHz) 01 = 83.33MHz Default (SPI SCL up to 12.5MHz, MDC up to 12MHz) 10 = 125MHz (for hign speed SPI about 25MHz) 11 = Reserved N/A Don't change. This bit is to enable PHY5, when in 10BT mode, to restore preamble before sending data on P5-MII interface. 1 = Enable PHY5 to restore preamble. 0 = Disable PHY5 to restore preamble. Tail Tag feature is applied for Port 5 only. 1 = Insert 1 Byte of data right before FCS. 0 = Do not insert. 1 = Switch will not filter 802.1x "flow control" packets. 0 = Switch will filter 802.1x "flow control" packets. R/W RO RO 0 1 Pin LED[2][2] strap option. PD(0): Select SW5-RMII at normal mode to receive external 50MHz RMII reference clock PU(1): (default) Select SW5RMII at clock mode, RMII output 50MHz Note: LED[2][2] has internal pullup. 01
3 2
Reserved Enable restore preamble
RO R/W
0 1
1 0
Tail Tag Enable Pass Flow Control Packet
R/W R/W
0 0
Register 13 (0x0D): Global Control 11
7-0 Factory Testing N/A Don't change. RO 00000000
Register 14 (0x0E): Power Down Management Control 1
7 6 Reserved Reserved N/A Don't change. N/A Don't change. RO RO 0 0
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Address 5 4-3
Name PLL Power Down Power Management Mode
Description Pll power down enable: 1 = Enable 0 = Disable Power management mode : 00 = Normal mode (D0) 01 = Energy Detection mode (D2) 10 = soft Power Down mode (D3) 11 = Power Saving mode (D1)
Mode R/W R/W
Default 0 00 Pin LED[4][0] strap option. PD(0): Select Energy detection mode PU(1): (default) Normal mode Note: LED[4][0] has internal pullup. 000
2-0
Reserved
N/A Don't change.
RO
Register 15 (0x0F): Power Down Management Control 2
7-0 Go_sleep_time[7:0] When the Energy Detect mode is on, this value is used to control the minimum period that the no energy event has to be detected consecutively before the device enters the low power state. The unit is 20 ms. The default of go_sleep time is 1.6 seconds (80Dec x 20ms). R/W 01010000
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Port Registers The following registers are used to enable features that are assigned on a per port basis. The register bit assignments are the same for all ports, but the address for each port is different, as indicated. Register 16 (0x10): Port 1 Control 0 Register 32 (0x20): Port 2 Control 0 Register 48 (0x30): Port 3 Control 0 Register 64 (0x40): Port 4 Control 0 Register 80 (0x50): Port 5 Control 0
Address 7 6 5 4-3 Name Broadcast Storm Protection Enable DiffServ Priority Classification Enable 802.1p Priority Classification Enable Port-Based Priority Classification Enable Description 1, enable broadcast storm protection for ingress packets on the port. 0, disable broadcast storm protection. 1, enable DiffServ priority classification for ingress packets on port. 0, disable DiffServ function. 1, enable 802.1p priority classification for ingress packets on port. 0, disable 802.1p. = 00, ingress packets on port will be classified as priority 0 queue if "Diffserv" or "802.1p" classification is not enabled or fails to classify. = 01, ingress packets on port will be classified as priority 1 queue if "Diffserv" or "802.1p" classification is not enabled or fails to classify. = 10, ingress packets on port will be classified as priority 2 queue if "Diffserv" or "802.1p" classification is not enabled or fails to classify. = 11, ingress packets on port will be classified as priority 3 queue if "Diffserv" or "802.1p" classification is not enabled or fails to classify. Note: "DiffServ", "802.1p" and port priority can be enabled at the same time. The OR'ed result of 802.1p and DSCP overwrites the port priority. 1, when packets are output on the port, the switch will add 802.1q tags to packets without 802.1q tags when received. The switch will not add tags to packets already tagged. The tag inserted is the ingress port's "port VID." 0, disable tag insertion. 1, when packets are output on the port, the switch will remove 802.1q tags from packets with 802.1q tags when received. The switch will not modify packets received without tags. 0, disable tag removal. Mode R/W R/W R/W R/W Default 0 0 0 00
2
Tag insertion
R/W
0
1
Tag Removal
R/W
0
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Address 0 Name Two Queues Split Enable Description This bit0 in the register16/32/48/64/80 should be in combination with Register177/193/209/225/241 bit 1 for Port 1-5 will select the split of 1/2/4 queues: For Port 1, [Register177 bit 1, Register16 bit 0] = [11], Reserved [10], the port output queue is split into four priority queues or if map 802.1p to priority 0-3 mode. [01], the port output queue is split into two priority queues or if map 802.1p to priority 0-3 mode. [00], single output queue on the port. There is no priority differentiation even though packets are classified into high or low priority.
KSZ8895MQ/RQ/FMQ
Mode R/W Default 0
Register 17 (0x11): Port 1 Control 1 Register 33 (0x21): Port 2 Control 1 Register 49 (0x31): Port 3 Control 1 Register 65 (0x41): Port 4 Control 1 Register 81 (0x51): Port 5 Control 1
Address 7 6 Name Sniffer Port Receive Sniff Description 1, port is designated as sniffer port and will transmit packets that are monitored. 0, port is a normal port. 1, all the packets received on the port will be marked as "monitored packets" and forwarded to the designated "sniffer port." 0, no receive monitoring. 1, all the packets transmitted on the port will be marked as "monitored packets" and forwarded to the designated "sniffer port." 0, no transmit monitoring. Define the port's Port VLAN membership. Bit 4 stands for Port 5, bit 3 for Port 4...bit 0 for Port 1. The port can only communicate within the membership. A `1' includes a port in the membership, a `0' excludes a port from membership. Mode R/W R/W Default 0 0
5
Transmit Sniff
R/W
0
4-0
Port VLAN Membership
R/W
0x1f
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Micrel, Inc. Register 18 (0x12): Port 1 Control 2 Register 34 (0x22): Port 2 Control 2 Register 50 (0x32): Port 3 Control 2 Register 66 (0x42): Port 4 Control 2 Register 82 (0x52): Port 5 Control 2
Address 7 Name User Priority Ceiling Description 1, If packet `s "user priority field" is greater than the "user priority field" in the port default tag register, replace the packet's "user priority field" with the "user priority field" in the port default tag register control 3. 0, no replace packet's priority filed with port default tag priority filed of the port register control 3 bit [7:5]. 1, the switch will discard packates whose VID port membership in VLAN table bit[20:16] does not include the ingress port. 0, no ingress VLAN filtering. 1, the switch will discard packets whose VID does not match ingress port default VID. 0, no packets will be discarded. 1, will always enable Rx and Tx flow control on the port, regardless of AN result. 0, the flow control is enabled based on AN result (Default)
KSZ8895MQ/RQ/FMQ
Mode R/W
Default 0
6
Ingress VLAN Filtering.
R/W
0
5 4
Discard Non-PVID packets Force Flow Control
R/W R/W
0 0 Strap-in option LED1_1/PCOL For port 3/port 4 LED1_1 default Pull up (1): Not force flow control; PCOL default Pull-down (0): Not force flow control. LED1_1 Pull down (0): Force flow control; PCOL Pull-up (1): Force flow control. Note: LED1_1 has internal pullup; PCOL have internal pull-down. Pin PMRXD2 strap option. Pull-down (0): disable back pressure. Pull-up(1): enable back pressure. Note: PMRXD2 has internal pulldown. 1 1 0
3
Back Pressure Enable
1, enable port half-duplex back pressure. 0, disable port half-duplex back pressure.
R/W
2 1 0
Note:
Transmit Enable Receive Enable Learning Disable
1, enable packet transmission on the port. 0, disable packet transmission on the port. 1, enable packet reception on the port. 0, disable packet reception on the port. 1, disable switch address learning capability. 0, enable switch address learning.
R/W R/W R/W
Bits 2-0 are used for spanning tree support. See "Spanning Tree Support" section.
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Micrel, Inc. Register 19 (0x13): Port 1 Control 3 Register 35 (0x23): Port 2 Control 3 Register 51 (0x33): Port 3 Control 3 Register 67 (0x43): Port 4 Control 3 Register 83 (0x53): Port 5 Control 3
Address 7-0 Name Default Tag [15:8] Description Port's default tag, containing: 7-5: user priority bits 4: CFI bit 3-0 : VID[11:8]
KSZ8895MQ/RQ/FMQ
Mode R/W
Default 0
Register 20 (0x14): Port 1 Control 4 Register 36 (0x24): Port 2 Control 4 Register 52 (0x34): Port 3 Control 4 Register 68 (0x44): Port 4 Control 4 Register 84 (0x54): Port 5 Control 4
Address 7-0
Note:
Name Default Tag [7:0]
Description Default port 1's tag, containing: 7-0: VID[7:0]
Mode R/W
Default 1
Registers 19 and 20 (and those corresponding to other ports) serve two purposes: (1) Associated with the ingress untagged packets, and used for egress tagging; (2) Default VID for the ingress untagged or null-VID-tagged packets, and used for address look up.
Register 87 (0x57): RMII Management Control Register
Address 7-4 3 Name Reserved Port 5 SW5-RMII 50MHz clock output disable (used for KSZ8895RQ only) Description N/A Don't change. Disable the output of port 5 SW5-RMII 50 MHz output clock on RXC pin when 50MHz clock is not being used by the device and the 50MHz clock from external oscillator or opposite device in RMII mode 1 = Disable clock output when RXC pin is not used in RMII mode 0 = Enable clock output in RMII mode Note:MQ/FMQ is reserved with read only for this bit. 2 P5-RMII 50MHz clock output disable (used for KSZ8895RQ only) Disable the output of port 5 P5-RMII 50 MHz output clock on RXC pin when 50MHz clock is not being used by the device and the 50MHz clock from external oscillator or opposite device in RMII mode 1 = Disable clock output when RXC pin is not used in RMII mode 0 = Enable clock output in RMII mode Note:MQ/FMQ is reserved with read only for this bit. 1-0 Reserved N/A Don't change. RO 00 R/W 0 Mode RO R/W Default 0000 0
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Micrel, Inc. Register 25 (0x19): Port 1 Status 0 Register 41 (0x29): Port 2 Status 0 Register 57 (0x39): Port 3 Status 0 Register 73 (0x49): Port 4 Status 0 Register 89 (0x59): Port 5 Status 0
Address 7 6 5 4 3 2 1 0 Name Hp_mdix Factory Testing Polrvs Transmit Flow Control Enable Receive Flow Control Enable Operation Speed Operation Duplex Reserved Description 1 = HP Auto MDI/MDI-X mode 0 = Micrel Auto MDI/MDI-X mode N/A Don't change. 1 = Polarity is reversed 0 = Polarity is not reversed 1 = Transmit flow control feature is active 0 = Transmit flow control feature is inactive 1 = Receive flow control feature is active 0 = Receive flow control feature is inactive 1 = Link speed is 100Mbps 0 = Link speed is 10Mbps 1 = Link duplex is full 0 = Link duplex is half N/A Don't change.
KSZ8895MQ/RQ/FMQ
Mode R/W RO RO RO RO RO RO RO
Default 1 0 0 0 0 0 0 0
Register 26 (0x1A): Port 1 PHY Special Control/Status Register 42 (0x2A): Port 2 PHY Special Control/Status Register 58 (0x3A): Port 3 PHY Special Control/Status Register 74 (0x4A): Port 4 PHY Special Control/Status Register 90 (0x5A): Port 5 PHY Special Control/Status
Address 7-4 3 2 1 Name Reserved Force_lnk Pwrsave Remote Loopback Description N/A Don't change. 1 = Force link pass 0 = Normal Operation 1 = Enable power saving 0 = Disable power saving 1 = Perform Remote loopback, loopback on port 1 as follows: Port 1 (reg. 26, bit 1 = `1') Start : RXP1/RXM1 (port 1) Loopback: PMD/PMA of port 1's PHY End: TXP1/TXM1 (port 1) Setting reg. 42, 58, 74, 90, bit 1 = `1' will perform remote loopback on port 2, 3, 4, 5. 0 = Normal Operation. N/A Don't change. Mode RO R/W R/W R/W Default 0000 0 0 0
0
Reserved
RO
0
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Micrel, Inc. Register 27 (0x1B): Reserved Register 43 (0x2B): Reserved Register 59 (0x3B): Reserved Register 75 (0x4B): Reserved Register 91 (0x5B): Reserved
Address 7-0 Name Reserved Description N/A Don't change.
KSZ8895MQ/RQ/FMQ
Mode RO
Default 0
Register 28 (0x1C): Port 1 Control 12 Register 44 (0x2C): Port 2 Control 12 Register 60 (0x3C): Port 3 Control 12 Register 76 (0x4C): Port 4 Control 12 Register 92 (0x5C): Port 5 Control 12
Address 7 Name Disable Auto-Negotiation Description 1, disable auto-negotiation, speed and duplex are decided by bit 6 and 5 of the same register. 0, auto-negotiation is on. Mode R/W Default 0 For Port 3/Port 4 only. INVERT of pins LED[2][1]/LED[5][0] strap option. PD(0): Disable Auto-Negotiation. PU(1): Enable Auto-Negotiation. Note: LED[2][1]/LED[5][0] have internal pull up. 1 0 For Port 3/Port 4 only. Pins LED1_0/PCRS strap option: 1). Force halfduplex mode: LED1_0 pin Pullup(1) (default) for Port 3 PCRS pin Pulldown (0) (default) for Port 4 2). Force fullDuplex mode: LED1_0 pin Pulldown(0) for Port 3 PCRS Pull-up (1) for Port 4. Note: LED1_0 has internal pull-up; PCRS have internal pull down.
Note: The register bit value is the INVERT of the strap value at the pin.
6 5
Forced Speed Forced Duplex
1, forced 100BT if AN is disabled (bit 7). 0, forced 10BT if AN is disabled (bit 7). 1, forced full-duplex if (1) AN is disabled or (2) AN is enabled but failed. 0, forced half-duplex if (1) AN is disabled or (2) AN is enabled but failed (Default).
R/W R/W
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Address 4 3 2 1 0 Name Advertised Flow Control Capability Advertised 100BT FullDuplex Capability Advertised 100BT HalfDuplex Capability Advertised 10BT FullDuplex Capability Advertised 10BT HalfDuplex Capability Description 1, advertise flow control capability. 0, suppress flow control capability from transmission to link partner. 1, advertise 100BT full-duplex capability. 0, suppress 100BT full-duplex capability from transmission to link partner. 1, advertise 100BT half-duplex capability. 0, suppress 100BT half-duplex capability from transmission to link partner. 1, advertise 10BT full-duplex capability. 0, suppress 10BT full-duplex capability from transmission to link partner. 1, advertise 10BT half-duplex capability. 0, suppress 10BT half-duplex capability from transmission to link partner.
KSZ8895MQ/RQ/FMQ
Mode R/W R/W R/W R/W R/W Default 1 1 1 1 1
Register 29 (0x1D): Port 1 Control 13 Register 45 (0x2D): Port 2 Control 13 Register 61 (0x3D): Port 3 Control 13 Register 77 (0x4D): Port 4 Control 13 Register 93 (0x5D): Port 5 Control 13
Address 7 Name LED Off Description 1, turn off all port's LEDs (LEDx_2, LEDx_1, LEDx_0, where "x" is the port number). These pins will be driven high if this bit is set to one. 0, normal operation. 1, disable port's transmitter. 0, normal operation. 1, restart auto-negotiation. 0, normal operation. N/A 1, power down. 0, normal operation. 1, disable auto MDI/MDI-X function. 0, enable auto MDI/MDI-X function. 1, if auto MDI/MDI-X is disabled, force PHY into MDI mode. 0, MDIX mode. 1 = Perform MAC loopback, loop back path as follows: E.g. set port 1 MAC Loopback (reg. 29, bit 0 = `1'), use port 2 as monitor port. The packets will transfer Start: Port 2 receiving (also can start to receive packets from port 3, 4, 5). Loop-back: Port 1's MAC. End: Port 2 transmitting (also can end at Port 3, 4, 5 respectively). Setting reg. 45, 61, 77, 93, bit 0 = `1' will perform MAC loopback on port 2, 3, 4, 5 respectively. 0 = Normal Operation. Mode R/W Default 0
6 5 4 3 2 1 0
Txids Restart AN FX reserved Power Down Disable Auto MDI/MDI-X Forced MDI MAC Loopback
R/W R/W (SC) RO R/W R/W R/W R/W
0 0 0 0 0 0 0
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Micrel, Inc. Register 30 (0x1E): Port 1 Status 1 Register 46 (0x2E): Port 2 Status 1 Register 62 (0x3E): Port 3 Status 1 Register 78 (0x4E): Port 4 Status 1 Register 94 (0x5E): Port 5 Status 1
Address 7 6 5 4 3 2 1 0 Name MDIX Status AN Done Link Good Partner Flow Control Capability Partner 100BT FullDuplex Capability Partner 100BT HalfDuplex Capability Partner 10BT Full-Duplex Capability Partner 10BT Half-Duplex Capability Description 1, MDI. 0, MDI-X. 1, AN done. 0, AN not done. 1, link good. 0, link not good. 1, link partner flow control capable. 0, link partner not flow control capable. 1, link partner 100BT full-duplex capable. 0, link partner not 100BT full-duplex capable. 1, link partner 100BT half-duplex capable. 0, link partner not 100BT half-duplex capable. 1, link partner 10BT full-duplex capable. 0, link partner not 10BT full-duplex capable. 1, link partner 10BT half-duplex capable. 0, link partner not 10BT half-duplex capable.
KSZ8895MQ/RQ/FMQ
Mode RO RO RO RO RO RO RO RO
Default 0 0 0 0 0 0 0 0
Register 31 (0x1F): Port 1 Control 14 and Status 2 Register 47 (0x2F): Port 2 Control 14 and Status 2 Register 63 (0x3F): Port 3 Control 14 and Status 2 Register 79 (0x4F): Port 4 Control 14 and Status 2 Register 95 (0x5F): Port 5 Control 14 and Status 2
Address 7 Name PHY Loopback Description 1 = Perform PHY loopback, loop back path as follows: E.g. set port 1 PHY Loopback (reg. 31, bit 7 = `1') Use the port 2 as monitor port. The packets will transfer. Start: Port 2 receiving (also can start from port 3, 4, 5). Loopback: PMD/PMA of Port 1's PHY End: Port 2 transmitting (also can end at Port 3, 4, 5 respectively). Setting reg. 47, 63, 79, 95, bit 7 = `1' will perform PHY loopback on port 2, 3, 4, 5 respectively. 0 = Normal Operation. Mode R/W Default 0
6 5 4 3
Reserved PHY Isolate Soft Reset Force Link 1, electrical isolation of PHY from MII/RMII and TX+/TX-. 0, normal operation. 1, PHY soft reset. This bit is self clear. 0, normal operation. 1, force link in the PHY. 0, normal operation
RO R/W R/W (SC) R/W
0 0 0 0
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Address 2-0 Name Port Operation Mode Indication Description Indicate the current state of port operation mode: [000] = Reseved [001] = still in auto-negotiation [010] = 10BASE-T half duplex [011] = 100BASE-TX half duplex [100] = Reserved [101] = 10BASE-T full duplex [110] = 100BASE-TX full duplex [111] = Reserved
KSZ8895MQ/RQ/FMQ
Mode RO Default 000
Note:
Port Control 12 and 13, 14 and Port Status 1,2 contents can be accessed by MIIM (MDC/MDIO) interface via the standard MIIM register definition.
Advanced Control Registers
Registers 104 to 109 define the switching engine's MAC address. This 48-bit address is used as the source address in MAC pause control frames.
Address
Name
Description
Mode
Default
Register 104 (0x68): MAC Address Register 0
7-0 MACA[47:40] R/W 0x00
Register 105 (0x69): MAC Address Register 1
7-0 MACA[39:32] R/W 0x10
Register 106 (0x6A): MAC Address Register 2
7-0 MACA[31:24] R/W 0xA1
Register 107 (0x6B): MAC Address Register 3
7-0 MACA[23:16] R/W 0xff
Register 108 (0x6C): MAC Address Register 4
7-0 MACA[15:8] R/W 0xff
Register 109 (0X6D): MAC Address Register 5
7-0 MACA[7:0] R/W 0xff
Use registers 110 and 111 to read or write data to the static MAC address table, VLAN table, dynamic address table, or the MIB counters.
Address
Name
Description
Mode
Default
Register 110 (0x6E): Indirect Access Control 0
7-5 4 3-2 Reserved Read High Write Low Table Select Reserved. 1, read cycle. 0, write cycle. 00 = static mac address table selected. 01 = VLAN table selected. 10 = dynamic address table selected. 11 = MIB counter selected. Bit 9-8 of indirect address. R/W R/W R/W 000 0 0
1-0
Indirect Address High
R/W
00
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Address Name Description
KSZ8895MQ/RQ/FMQ
Mode Default
Register 111 (0x6F): Indirect Access Control 1
7-0 Indirect Address Low Bit 7-0 of indirect address. R/W 00000000
Note: Write to Register 111 will actually trigger a command. Read or write access will be decided by bit 4 of Register 110.
Address
Name
Description
Mode
Default
Register 112 (0x70): Indirect Data Register 8
68-64 Indirect Data Bit 68-64 of indirect data. R/W 00000
Register 113 (0x71): Indirect Data Register 7
63-56 Indirect Data Bit 63-56 of indirect data. R/W 00000000
Register 114 (0x72): Indirect Data Register 6
55-48 Indirect Data Bit 55-48 of indirect data. R/W 00000000
Register 115 (0x73): Indirect Data Register 5
47-40 Indirect Data Bit 47-40 of indirect data. R/W 00000000
Register 116 (0x74): Indirect Data Register 4
39-32 Indirect Data Bit 39-32 of indirect data. R/W 00000000
Register 117 (0x75): Indirect Data Register 3
31-24 Indirect Data Bit of 31-24 of indirect data R/W 00000000
Register 118 (0x76): Indirect Data Register 2
23-16 Indirect Data Bit 23-16 of indirect data. R/W 00000000
Register 119 (0x77): Indirect Data Register 1
15-8 Indirect Data Bit 15-8 of indirect data. R/W 00000000
Register 120 (0x78): Indirect Data Register 0
7-0 Indirect Data Bit 7-0 of indirect data. R/W 00000000
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Address
Name
Description
Mode
Default
Register 124 (0x7C): Interrupt Status Register
7-5 4 Reserved Port 5 Interrupt Status Reserved. 1, Port 5 interrupt request 0, normal Note: This bit is set by Port 5 link change. Write a "1" to clear this bit 1, Port 4 interrupt request 0, normal Note: This bit is set by Port 4 link change. Write a "1" to clear this bit 1, Port 3 interrupt request 0, normal Note: This bit is set by Port 3 link change. Write a "1" to clear this bit 1, Port 2 interrupt request 0, normal Note: This bit is set by Port 2 link change. Write a "1" to clear this bit 1, Port 1 interrupt request 0, normal Note: This bit is set by Port 1 link change. Write a "1" to clear this bit RO RO 000 0
3
Port 4 Interrupt Status
RO
0
2
Port 3 Interrupt Status
RO
0
1
Port 2 Interrupt Status
RO
0
0
Port 1 Interrupt Status
RO
0
Register 125 (0x7D): Interrupt Mask Register
7-5 4 3 2 1 0 Reserved Port 5 Interrupt Mask Port 4 Interrupt Mask Port 3 Interrupt Mask Port 2 Interrupt Mask Port 1 Interrupt Mask Reserved. 1, Port 5 interrupt mask 0, normal 1, Port 4 interrupt mask 0, normal 1, Port 3 interrupt mask 0, normal 1, Port 2 interrupt mask 0, normal 1, Port 1 interrupt mask 0, normal RO R/W R/W R/W R/W R/W 000 0 0 0 0 0
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The registers 128, 129 can be used to map from 802.1p priority field 0-7 to switch's four priority queues 0-3, 0x3 is highest priority queues as priority 3, 0x0 is lowest priority queues as priority 0. Address Name Description Mode Default
Register 128 (0x80): Global Control 12
7-6 5-4 3-2 1-0 Tag_0x3 Tag_0x2 Tag_0x1 Tag_0x0 IEEE 802.1p mapping. The value in this field is used as the frame's priority when its IEEE 802.1p tag has a value of 0x3. IEEE 802.1p mapping. The value in this field is used as the frame's priority when its IEEE 802.1p tag has a value of 0x2. IEEE 802.1p mapping. The value in this field is used as the frame's priority when its IEEE 802.1p tag has a value of 0x1. IEEE 802.1p mapping. The value in this field is used as the frame's priority when its IEEE 802.1p tag has a value of 0x0. R/W R/W R/W R/W 0x1 0x1 0x0 0x0
Register 129 (0x81): Global Control 13
7-6 5-4 3-2 1-0 Tag_0x7 Tag_0x6 Tag_0x5 Tag_0x4 IEEE 802.1p mapping. The value in this field is used as the frame's priority when its IEEE 802.1p tag has a value of 0x7. IEEE 802.1p mapping. The value in this field is used as the frame's priority when its IEEE 802.1p tag has a value of 0x6. IEEE 802.1p mapping. The value in this field is used as the frame's priority when its IEEE 802.1p tag has a value of 0x5. IEEE 802.1p mapping. The value in this field is used as the frame's priority when its IEEE 802.1p tag has a value of 0x4. R/W R/W R/W R/W 0x3 0x3 0x2 0x2
Register 130 (0x82): Global Control 14
7-6 Pri_2Q[1:0] (Note that program Prio_2Q[1:0] = 01 is not supported and should be avoided) When the 2 Queues configuration is selected, these Pri_2Q[1:0] bits are used to map the 2-bit result of IEEE 802.1p from register 128/129 or TOS/DiffServ from register 144- 159 mapping (for 4 Queues) into two queues low/high priorities. 2-bit result of IEEE 802.1p or TOS/DiffServ 00 (0) = map to Low priority queue 01 (1) = Prio_2Q[0] map to Low/High priority queue 10 (2) = Prio_2Q[1] map to Low/High priority queue 11 (3) = map to High priority queue Pri_2Q[1:0] = 00: Result 0,1,2 are low priority. 3 is high priority. 10: Result 0,1 are low priority. 2,3 are high priority (default). 11: Result 0 is low priority. 1,2,3 are high priority. 5 4 3-2 1 0 Reserved Reserved Reserved Reserved Reserved N/A Don't change. N/A Don't change. N/A Don't change. N/A Don't change. N/A Don't change. RO RO RO RO RO 0 0 01 0 0. R/W 10
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Address Name Description
KSZ8895MQ/RQ/FMQ
Mode Default
Register 131 (0x83): Global Control 15
7 6 5 4-0 Reserved Reserved Unknown unicast packet forward Unknown unicast packet forward port map N/A N/A 1 = enable supporting unknown unicast packet forward 0 = disable 00000 = filter uknown unicast packet 00001 = forward uknown unicast packet to port 1 00011 = forward uknown unicast packet to port 1, port 2 ... 11111 = broadcast uknown unicast packet to all ports RO RO R/W R/W 0 0 0 00000
Register 132 (0x84): Global Control 16
7-6 Chip I/O output drive strength select[1:0] Output drive strength select[1:0] = 00 = 4mA drive strength 01 = 8mA drive strength (default) 10 = 12mA drive strength 11 = 16 mA drive strength Note: bit[1] value is the INVERT of the strap value at the pin. Bit[0] value is the SAME of the strap value at the pin 5 4-0 Unknown multicast packet forward (not including IP multicast packet) Unknown multicast packet forward port map 1 = enable supporting unknown multicast packet forward 0 = disable 00000 = filter uknown multiicast packet 00001 = forward uknown multicast packet to port 1 00011 = forward uknown multicast packet to port 1, port 2 ... 11111 = broadcast uknown multicast packet to all ports R/W R/W R/W 01 Pin LED[3][0] strap option. Pull-down (0): Select 12mA drive strength. Pull-up (1): Select 8mA drive strength. Note: LED[3][0] has internal pull-up. 0 00000
Register 133(0x85): Global Control 17
7-6 5 4-0 Reserved Unknown VID packet forward Unknown VID packet forward port map 1 = enable supporting unknown VID packet forward 0 = disable 00000 = filter uknown VID packet 00001 = forward uknown VID packet to port 1 00011 = forward uknown VID packet to port 1, port 2 ... 11111 = broadcast uknown VID packet to all ports RO R/W R/W 00 0 00000
Register 134 (0x86): Global Control 18
7 6 Reserved Self Address Filter Enable N/A 1 = Enable filtering of self-address unicast and multicast packet 0 = Do not filter self-address packet RO R/W 0 0
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Address 5 4-0 Name Unknown IP multicast packet forward Unknown IP multicast packet forward port map Description 1 = enable supporting unknown IP multicast packet forward 0 = disable 00000 = filter uknown IP multiicast packet 00001 = forward uknown IP multicast packet to port 1 00011 = forward uknown IP multicast packet to port 1, port 2 ... 11111 = broadcast uknown IP multicast packet to all ports
KSZ8895MQ/RQ/FMQ
Mode R/W R/W Default 0 00000
Register 135 (0x87): Global Control 19
7 6 5-4 Reserved Reserved Ingress Rate Limit Period N/A Don't change. N/A Don't change. The unit period for calculating Ingress Rate Limit 00 = 16 ms 01 = 64 ms 1x = 256 ms Enable Queue-based Egress Rate Limit 0 = port-base Egress Rate Limit (default) 1 = queue-based Egress Rate Limit 1 = enable source port PVID tag insertion or noninsertion option on the egress port for each source port PVID based on the ports registers control 8. 0 = disable, all packets from any ingress port will be inserted PVID based on port register control 0 bit 2. N/A Don't change RO RO R/W 0 0 01
3 2
Queue-based Egress Rate Limit Enabled Insertion Source Port PVID Tag Selection Enable
R/W R/W
0 0
1-0
Reserved
RO
00
Register 144 (0x90): TOS Priority Control Register 0
The Ipv4/Ipv6 TOS priority control registers implement a fully decoded 64 bit differentiated services code point (DSCP) register used to determine priority from the 6 bit TOS field in the IP header. The most significant 6 bits of the TOS field are fully decoded into 64 possibilities, and the singular code that results is mapped to the value in the corresponding bit in the DSCP register.
7-6
DSCP[7:6]
5-4
DSCP[5:4]
3-2
DSCP[3:2]
1-0
DSCP[1:0]
Ipv4 and Ipv6 mapping The value in this field is used as the frame's priority when bits[7:2] of the frame's IP TOS/DiffServ/Traffic Class value is 0x03 Ipv4 and Ipv6 mapping The value in this field is used as the frame's priority when bits[7:2] of the frame's IP TOS/DiffServ/Traffic Class value is 0x02 Ipv4 and Ipv6 mapping The value in this field is used as the frame's priority when bits[7:2] of the frame's IP TOS/DiffServ/Traffic Class value is 0x01 Ipv4 and Ipv6 mapping The value in this field is used as the frame's priority when bits[7:2] of the frame's IP TOS/DiffServ/Traffic Class value is 0x00
R/W
00
R/W
00
R/W
00
R/W
00
Register 145 (0x91): TOS Priority Control Register 1
7-6 5-4 3-2 1-0 DSCP[15:14] DSCP[13:12] DSCP[11:10] DSCP[9:8] Ipv4 and Ipv6 mapping _ for value 0x07 Ipv4 and Ipv6 mapping _ for value 0x06 Ipv4 and Ipv6 mapping _ for value 0x05 Ipv4 and Ipv6 mapping _ for value 0x04 R/W R/W R/W R/W 00 00 00 00
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Address Name Description
KSZ8895MQ/RQ/FMQ
Mode Default
Register 146 (0x92): TOS Priority Control Register 2
7-6 5-4 3-2 1-0 DSCP[23:22] DSCP[21:20] DSCP[19:18] DSCP[17:16] Ipv4 and Ipv6 mapping _ for value 0x0B Ipv4 and Ipv6 mapping _ for value 0x0A Ipv4 and Ipv6 mapping _ for value 0x09 Ipv4 and Ipv6 mapping _ for value 0x08 R/W R/W R/W R/W 00 00 00 00
Register 147 (0x93): TOS Priority Control Register 3
7-6 5-4 3-2 1-0 DSCP[31:30] DSCP[29:28] DSCP[27:26] DSCP[25:24] Ipv4 and Ipv6 mapping _ for value 0x0F Ipv4 and Ipv6 mapping _ for value 0x0E Ipv4 and Ipv6 mapping _ for value 0x0D Ipv4 and Ipv6 mapping _ for value 0x0C R/W R/W R/W R/W 00 00 00 00
Register 148 (0x94): TOS Priority Control Register 4
7-6 5-4 3-2 1-0 DSCP[39:38] DSCP[37:36] DSCP[35:34] DSCP[33:32] Ipv4 and Ipv6 mapping _ for value 0x13 Ipv4 and Ipv6 mapping _ for value 0x12 Ipv4 and Ipv6 mapping _ for value 0x11 Ipv4 and Ipv6 mapping _ for value 0x10 R/W R/W R/W R/W 00 00 00 00
Register 149 (0x95): TOS Priority Control Register 5
7-6 5-4 3-2 1-0 DSCP[47:46] DSCP[45:44] DSCP[43:42] DSCP[41:40] Ipv4 and Ipv6 mapping _ for value 0x17 Ipv4 and Ipv6 mapping _ for value 0x16 Ipv4 and Ipv6 mapping _ for value 0x15 Ipv4 and Ipv6 mapping _ for value 0x14 R/W R/W R/W R/W 00 00 00 00
Register 150 (0x96): TOS Priority Control Register 6
7-6 5-4 3-2 1-0 DSCP[55:54] DSCP[53:52] DSCP[51:50] DSCP[49:48] Ipv4 and Ipv6 mapping _ for value 0x1B Ipv4 and Ipv6 mapping _ for value 0x1A Ipv4 and Ipv6 mapping _ for value 0x19 Ipv4 and Ipv6 mapping _ for value 0x18 R/W R/W R/W R/W 00 00 00 00
Register 151 (0x97): TOS Priority Control Register 7
7-6 5-4 3-2 1-0 DSCP[63:62] DSCP[61:60] DSCP[59:58] DSCP[57:56] Ipv4 and Ipv6 mapping _ for value 0x1F Ipv4 and Ipv6 mapping _ for value 0x1E Ipv4 and Ipv6 mapping _ for value 0x1D Ipv4 and Ipv6 mapping _ for value 0x1C R/W R/W R/W R/W 00 00 00 00
Register 152 (0x98): TOS Priority Control Register 8
7-6 5-4 3-2 1-0 DSCP[71:70] DSCP[69:68] DSCP[67:66] DSCP[65:64] Ipv4 and Ipv6 mapping _ for value 0x23 Ipv4 and Ipv6 mapping _ for value 0x22 Ipv4 and Ipv6 mapping _ for value 0x21 Ipv4 and Ipv6 mapping _ for value 0x20 R/W R/W R/W R/W 00 00 00 00
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Address Name Description
KSZ8895MQ/RQ/FMQ
Mode Default
Register 153 (0x99): TOS Priority Control Register 9
7-6 5-4 3-2 1-0 DSCP[79:78] DSCP[77:76] DSCP[75:74] DSCP[73:72] Ipv4 and Ipv6 mapping _ for value 0x27 Ipv4 and Ipv6 mapping _ for value 0x26 Ipv4 and Ipv6 mapping _ for value 0x25 Ipv4 and Ipv6 mapping _ for value 0x24 R/W R/W R/W R/W 00 00 00 00
Register 154 (0x9A): TOS Priority Control Register 10
7-6 5-4 3-2 1-0 DSCP[87:86] DSCP[85:84] DSCP[83:82] DSCP[81:80] Ipv4 and Ipv6 mapping _ for value 0x2B Ipv4 and Ipv6 mapping _ for value 0x2A Ipv4 and Ipv6 mapping _ for value 0x29 Ipv4 and Ipv6 mapping _ for value 0x28 R/W R/W R/W R/W 00 00 00 00
Register 155 (0x9B): TOS Priority Control Register 11
7-6 5-4 3-2 1-0 DSCP[95:94] DSCP[93:92] DSCP[91:90] DSCP[89:88] Ipv4 and Ipv6 mapping _ for value 0x2F Ipv4 and Ipv6 mapping _ for value 0x2E Ipv4 and Ipv6 mapping _ for value 0x2D Ipv4 and Ipv6 mapping _ for value 0x2C R/W R/W R/W R/W 00 00 00 00
Register 156 (0x9C): TOS Priority Control Register 12
7-6 5-4 3-2 1-0 DSCP[103:102] DSCP[101:100] DSCP[99:98] DSCP[97:96] Ipv4 and Ipv6 mapping _ for value 0x33 Ipv4 and Ipv6 mapping _ for value 0x32 Ipv4 and Ipv6 mapping _ for value 0x31 Ipv4 and Ipv6 mapping _ for value 0x30 R/W R/W R/W R/W 00 00 00 00
Register 157 (0x9D): TOS Priority Control Register 13
7-6 5-4 3-2 1-0 DSCP[111:110] DSCP[109:108] DSCP[107:106] DSCP[105:104] Ipv4 and Ipv6 mapping _ for value 0x37 Ipv4 and Ipv6 mapping _ for value 0x36 Ipv4 and Ipv6 mapping _ for value 0x35 Ipv4 and Ipv6 mapping _ for value 0x34 R/W R/W R/W R/W 00 00 00 00
Register 158 (0x9E): TOS Priority Control Register 14
7-6 5-4 3-2 1-0 DSCP[119:118] DSCP[117:116] DSCP[115:114] DSCP[113:112] Ipv4 and Ipv6 mapping _ for value 0x3B Ipv4 and Ipv6 mapping _ for value 0x3A Ipv4 and Ipv6 mapping _ for value 0x39 Ipv4 and Ipv6 mapping _ for value 0x38 R/W R/W R/W R/W 00 00 00 00
Register 159 (0x9F): TOS Priority Control Register 15
7-6 5-4 3-2 1-0 DSCP[127:126] DSCP[125:124] DSCP[123:122] DSCP[121:120] Ipv4 and Ipv6 mapping _ for value 0x3F Ipv4 and Ipv6 mapping _ for value 0x3E Ipv4 and Ipv6 mapping _ for value 0x3D Ipv4 and Ipv6 mapping _ for value 0x3C R/W R/W R/W R/W 00 00 00 00
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Address Name Description
KSZ8895MQ/RQ/FMQ
Mode Default
Register 176 (0xB0): Port 1 Control 8 Register 192 (0xC0): Port 2 Control 8 Register 208 (0xD0): Port 3 Control 8 Register 224 (0xE0): Port 4 Control 8 Register 240 (0xF0): Port 5 Control 8
7-4
3
Reserved Insert Source Port PVID for Untagged Packet Destination to Highest Egress Port Note: Enabled by the register 135 bit 2 Register 176: insert source Port 1 PVID for untagged frame at egress Port 5 Register 192: insert source Port 2 PVID for untagged frame at egress Port 5 Register 208: insert source Port 3 PVID for untagged frame at egress Port 5 Register 224: insert source Port 4 PVID for untagged frame at egress Port 5 Register 240: insert source Port 5 PVID for untagged frame at egress Port 4 Register 176: insert source Port 1 PVID for untagged frame at egress pPort 4 Register 192: insert source Port 2 PVID for untagged frame at egress Port 4 Register 208: insert source Port 3 PVID for untagged frame at egress Port 4 Register 224: insert source Port 4 PVID for untagged frame at egress Port 3 Register 240: insert source Port 5 PVID for untagged frame at egress Port 3 Register 176: insert source Port 1 PVID for untagged frame at egress Port 3 Register 192: insert source Port 2 PVID for untagged frame at egress Port 3 Register 208: insert source Port 3 PVID for untagged frame at egress Port 2 Register 224: insert source Port 4 PVID for untagged frame at egress Port 2 Register 240: insert source Port 5 PVID for untagged frame at egress Port 2 Register 176: insert source Port 1 PVID for untagged frame at egress Port 2 Register 192: insert source Port 2 PVID for untagged frame at egress Port 1 Register 208: insert source Port 3 PVID for untagged frame at egress Port 1 Register 224: insert source Port 4 PVID for untagged frame at egress Port 1 Register 240: insert source Port 5 PVID for untagged frame at egress Port 1
RO
R/W
0000
0
2
Insert Source Port PVID for Untagged Packet Destination to Second Highest Egress Port Note: Enabled by the register 135 bit 2
R/W
0
1
Insert Source Port PVID for Untagged Packet Destination to Second Lowest Egress Port Note: Enabled by the register 135 bit 2
R/W
0
0
Insert Source Port PVID for Untagged Packet Destination to Lowest Egress Port Note: Enabled by the register 135 bit 2
R/W
0
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Address Name Description
KSZ8895MQ/RQ/FMQ
Mode Default
Register 177 (0xB1): Port 1 Control 9 Register 193 (0xC1): Port 2 Control 9 Register 209 (0xD1): Port 3 Control 9 Register 225 (0xE1): Port 4 Control 9 Register 241 (0xF1): Port 5 Control 9
7-2
1
Reserved 4 Queue Split Enable This bit in combination with Register16/32/48/64/80 bit 0 will select the split of 1/2/4 queues: {Register177 bit 1, Register16 bit 0}= 11, reserved. 10, the port output queue is split into four priority queues or if map 802.1p to priority 0-3 mode. 01, the port output queue is split into two priority queues or if map 802.1p to priority 0-3 mode. 00, single output queue on the port. There is no priority differentiation even though packets are classified into high and low priority. 0 = disable tag drop 1 = enable tag drop
RO
R/W
0000000
0
0
Enable Dropping Tag
R/W
0
Register 178 (0xB2): Port 1 Control 10 Register 194 (0xC2): Port 2 Control 10 Register 210 (0xD2): Port 3 Control 10 Register 226 (0xE2): Port 4 Control 10 Register 242 (0xF2): Port 5 Control 10
7
Enable Port Transmit Queue 3 Ratio
6-0
Port Transmit Queue 3 Ratio[6:0]
0, strict priority, will transmit all the packets from this priority queue 3 before transmit lower priority queue. 1, bit[6:0] reflect the packet number allow to transmit from this priority queue 3 within a certain time. Packet number for Transmit Queue 3 for highest priority packets in four queues mode.
R/W
1
R/W
0001000
Register 179 (0xB3): Port 1 Control 11 Register 195 (0xC3): Port 2 Control 11 Register 211 (0xD3): Port 3 Control 11 Register 227 (0xE3): Port 4 Control 11 Register 243 (0xF3): Port 5 Control 11
7
Enable Port Transmit Queue 2 Ratio
6-0
Port Transmit Queue 2 Ratio[6:0]
0, strict priority, will transmit all the packets from this priority queue 2 before transmit lower priority queue. 1, bit[6:0] reflect the packet number allow to transmit from this priority queue 1 within a certain time. Packet number for Transmit Queue 2 for high/low priority packets in high/low priority packets in four queues mode.
R/W
1
R/W
0000100
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Address Name Description
KSZ8895MQ/RQ/FMQ
Mode Default
Register 180 (0xB4): Port 1 Control 12 Register 196 (0xC4): Port 2 Control 12 Register 212 (0xD4): Port 3 Control 12 Register 228 (0xE4): Port 4 Control 12 Register 244 (0xF4): Port 5 Control 12
7
Enable Port Transmit Queue 1 Rate
0, strict priority, will transmit all the packets from this priority queue 1 before transmit lower priority queue. 1, bit[6:0] reflect the packet number allow to transmit from this priority queue 1 within a certain time. Packet number for Transmit Queue 1 for low/high priority packets in four queues mode and high priority packets in two queues mode.
R/W
1
6-0
Port Transmit Queue 1 Ratio[6:0]
R/W
0000010
Register 181 (0xB5): Port 1 Control 13 Register 197 (0xC5): Port 2 Control 13 Register 213 (0xD5): Port 3 Control 13 Register 229 (0xE5): Port 4 Control 13 Register 245 (0xF5): Port 5 Control 13
7
Enable Port Transmit Queue 0 Rate
0, strict priority, will transmit all the packets from this priority queue 0 before transmit lower priority queue. 1, bit[6:0] reflect the packet number allow to transmit from this priority queue 0 within a certain time. packet number for Transmit Queue 0 for lowest priority packets in four queues mode and low priority packets in two queues mode.
R/W
1
6-0
Port Transmit Queue 0 Ratio[6:0]
R/W
0000001
Register 182 (0xB6): Port 1 Rate Limit Control Register 198 (0xC6): Port 2 Rate Limit Control Register 214 (0xD6): Port 3 Rate Limit Control Register 230 (0xE6): Port 4 Rate Limit Control Register 246 (0xF6): Port 5 Rate Limit Control
7-5 4 Reserved Ingress Rate Limit Flow Control Enable Limit Mode 1 = Flow Control is asserted if the port's receive rate is exceeded. 0 = Flow Control is not asserted if the port's receive rate is exceeded. Ingress Limit Mode These bits determine what kinds of frames are limited and counted against ingress rate limiting. = 00, limit and count all frames. = 01, limit and count Broadcast, Multicast, and flooded unicast frames. = 10, limit and count Broadcast and Multicast frames only. = 11, limit and count Broadcast frames only. RO R/W 000 0
3-2
R/W
00
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Address 1 Name Count IFG Description Count IFG bytes = 1, each frame's minimum inter frame gap. (IFG) bytes (12 per frame) are included in Ingress and Egress rate limiting calculations. = 0, IFG bytes are not counted. Count Preamble bytes = 1, each frame's preamble bytes (8 per frame) are included in Ingress and Egress rate limiting calculations. = 0, preamble bytes are not counted.
KSZ8895MQ/RQ/FMQ
Mode R/W Default 0
0
Count Pre
R/W
0
Register 183 (0xB7): Port 1 Priority 0 Ingress Limit Control 1 Register 199 (0xC7): Port 2 Priority 0 Ingress Limit Control 1 Register 215 (0xD7): Port 3 Priority 0 Ingress Limit Control 1 Register 231 (0xE7): Port 4 Priority 0 Ingress Limit Control 1 Register 247 (0xF7): Port 5 Priority 0 Ingress Limit Control 1
7 6-0 Reserved Port Based Priority 0 Ingress Limit Ingress data rate limit for priority 0 frames Ingress traffic from this port is shaped according to the Data Rate Selected Table. See the table follow the end of Egress limit control registers. RO R/W 0 0000000
Register 184 (0xB8): Port 1 Priority 1 Ingress Limit Control 2 Register 200 (0xC8): Port 2 Priority 1 Ingress Limit Control 2 Register 216 (0xD8): Port 3 Priority 1 Ingress Limit Control 2 Register 232 (0xE8): Port 4 Priority 1 Ingress Limit Control 2 Register 248 (0xF8): Port 5 Priority 1 Ingress Limit Control 2
7 6-0 Reserved Port Based Priority 1 Ingress Limit Ingress data rate limit for priority 1 frames Ingress traffic from this port is shaped according to the Data Rate Selected Table. See the table follow the end of Egress limit control registers. RO R/W 0 0000000
Register 185 (0xB9): Port 1 Priority 2 Ingress Limit Control 3 Register 201 (0xC9): Port 2 Priority 2 Ingress Limit Control 3 Register 217 (0xD9): Port 3 Priority 2 Ingress Limit Control 3 Register 233 (0xE9): Port 4 Priority 2 Ingress Limit Control 3 Register 249 (0xF9): Port 5 Priority 2 Ingress Limit Control 3
7 6-0 Reserved Port Based Priority 2 Ingress Limit Ingress data rate limit for priority 2 frames Ingress traffic from this port is shaped according to the Data Rate Selected Table. See the table follow the end of Egress limit control registers. RO R/W 0 0000000
Register 186 (0xBA): Port 1 Priority 3 Ingress Limit Control 4 Register 202 (0xCA): Port 2 Priority 3 Ingress Limit Control 4 Register 218 (0xDA): Port 3 Priority 3 Ingress Limit Control 4 Register 234 (0xEA): Port 4 Priority 3 Ingress Limit Control 4 Register 250 (0xFA): Port 5 Priority 3 Ingress Limit Control 4
7 Reserved RO 0 M9999-012011-1.2
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Address 6-0 Name Port Based Priority 3 Ingress Limit Description Ingress data rate limit for priority 3 frames Ingress traffic from this port is shaped according to the Data Rate Selected Table. See the table follow the end of Egress limit control registers.
KSZ8895MQ/RQ/FMQ
Mode R/W Default 0000000
Register 187 (0xBB): Port 1 Queue 0 Egress Limit Control 1 Register 203 (0xCB): Port 2 Queue 0 Egress Limit Control 1 Register 219 (0xDB): Port 3 Queue 0 Egress Limit Control 1 Register 235 (0xEB): Port 4 Queue 0 Egress Limit Control 1 Register 251 (0xFB): Port 5 Queue 0 Egress Limit Control 1
7 6-0 Reserved Port Queue 0 Egress Limit Egress data rate limit for priority 0 frames Egress traffic from this priority queue is shaped according to the Data Rate Selected Table. See the table follow the end of Egress limit control registers. In four queues mode, it is lowest priority. In two queues mode, it is low priority. RO R/W 0 0000000
Register 188 (0xBC) : Port 1 Queue 1 Egress Limit Control 2 Register 204 (0xCC) : Port 2 Queue 1 Egress Limit Control 2 Register 220 (0xDC) : Port 3 Queue 1 Egress Limit Control 2 Register 236 (0xEC) : Port 4 Queue 1 Egress Limit Control 2 Register 252 (0xFC) : Port 5 Queue 1 Egress Limit Control 2
7 6-0 Reserved Port Queue 1 Egress Limit Egress data rate limit for priority 1 frames Egress traffic from this priority queue is shaped according to the Data Rate Selected Table. See the table follow the end of Egress limit control registers. In four queues mode, it is low/high priority. In two queues mode, it is high priority. RO R/W 0 0000000
Register 189 (0xBD): Port 1 Queue 2 Egress Limit Control 3 Register 205 (0xCD): Port 2 Queue 2 Egress Limit Control 3 Register 221 (0xDD): Port 3 Queue 2 Egress Limit Control 3 Register 237 (0xED): Port 4 Queue 2 Egress Limit Control 3 Register 253 (0xFD): Port 5 Queue 2 Egress Limit Control 3
7 6-0 Reserved Port Queue 2 Egress Limit Egress data rate limit for priority 2 frames Egress traffic from this priority queue is shaped according to the Data Rate Selected Table. See the table follow the end of Egress limit control registers. In four queues mode, it is high/low priority. RO R/W 0 0000000
Register 190 (0xBE) : Port 1 Queue 3 Egress Limit Control 4 Register 206 (0xCE) : Port 2 Queue 3 Egress Limit Control 4 Register 222 (0xDE) : Port 3 Queue 3 Egress Limit Control 4 Register 238 (0xEE): Port 4 Queue 3 Egress Limit Control 4 Register 254 (0xFE): Port 5 Queue 3 Egress Limit Control 4 January 2011 85
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Address 7 6-0 Name Reserved Port Queue 3 Egress Limit Egress data rate limit for priority 3 frames Egress traffic from this priority queue is shaped according to the Data Rate Selected Table. See the table follow the end of Egress limit control registers. In four queues mode, it is highest priority. Description
KSZ8895MQ/RQ/FMQ
Mode RO R/W Default 0 0000000
Note: 1. In the port priority 0-3 ingress rate limit mode, will need to set all related ingress/egress ports to two queues or four queues mode. 2. In the port queue 0-3 egress rate limit mode, the highest priority get exact rate limit based on the rate select table, other priorities packets rate are based up on the ratio of the port register control 10/11/12/13 when use more than one egress queue per port.
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Rate for 100BT mode 1 Mbps <= rate <= 99 Mbps rate = 100 Mbps Less than 1Mbps see as below 64 Kbps 128 Kbps 192 Kbps 256 Kbps 320 Kbps 384 Kbps 448 Kbps 512 Kbps 576 Kbps 640 Kbps 704 Kbps 768 Kbps 832 Kbps 896 Kbps 960 Kbps
KSZ8895MQ/RQ/FMQ
Priority/Queue 0-3 Ingress/egress limit Control Register bit[6:0]= decimal rate(decimal integer 1-99) 0 or 100 (decimal), `0' is default value Decimal 7'd101 7'd102 7'd103 7'd104 7'd105 7'd106 7'd107 7'd108 7'd109 7'd110 7'd111 7'd112 7'd113 7'd114 7'd115 Table 13. 100BT Rate Selection for the Rate limit
Data Rate Selection Table in 10BT
Rate for 10BT mode 1 Mbps <= rate <= 9 Mbps rate = 10 Mbps Less than 1Mbps see as below 64 Kbps 128 Kbps 192 Kbps 256 Kbps 320 Kbps 384 Kbps 448 Kbps 512 Kbps 576 Kbps 640 Kbps 704 Kbps 768 Kbps 832 Kbps 896 Kbps 960 Kbps Priority/Queue 0-3 Ingress/egress limit Control Register bit[6:0]= decimal rate(decimal integer 1-9) 0 or 10 (decimal), `0' is default value Decimal 7'd101 7'd102 7'd103 7'd104 7'd105 7'd106 7'd107 7'd108 7'd109 7'd110 7'd111 7'd112 7'd113 7'd114 7'd115 Table 14. 10BT Rate Selection for the Rate Limit
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KSZ8895MQ/RQ/FMQ
Address
Name
Description
Mode
Default
Register 191(0xBF): Testing Register
7-0 Reserved N/A RO 00000000
Register 207(0xCF): Reserved Control Register
7-0 Reserved
N/A Don't change.
RO
0x15
Register 223(0xDF): Test Register 2
7-0 Reserved R/W 00000000
Register 239(0xEF): Test Register 3
7 6 5 4-0 Reserved Reserved Reserved Reserved
N/A Don't change. N/A Don't change. N/A Don't change. N/A Don't change.
RO RO RO RO
0 0 1 0x12
Register 255(0xFF): Testing Register4
7 6 Reserved Invert phase of SMTXC clock input for SW5-RMII (Used for KSZ8895RQ only)
N/A Don't change.
RO R/W
0 0
1 = Invert the phase of SMTXC clock input in RMII mode, set this bit at normal mode device when connect two devices with SW5-RMII back to back connection case only. Please see strap pin LED2_2 for normal mode. 0 = normal phase if SMTXC clock input Note: MQ/FMQ are reserved with read only for this bit.
5-0
Reserved
N/A Don't change.
RO
000000
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Static MAC Address Table
KSZ8895MQ/RQ/FMQ has a static and a dynamic address table. When a DA look-up is requested, both tables will be searched to make a packet forwarding decision. When an SA look-up is requested, only the dynamic table is searched for aging, migration, and learning purposes. The static DA look-up result will have precedence over the dynamic DA look-up result. If there are DA matches in both tables, the result from the static table will be used. The static table can only be accessed and controlled by an external SPI master (usually a processor). The entries in the static table will not be aged out by KSZ8895MQ/RQ/FMQ. An external device does all addition, modification and deletion.
Note: Register bit assignments are different for static MAC table reads and static MAC table write, as shown in the two tables below.
Address
Name
Description
Mode
Default
Format of Static MAC Table for Reads (32 entries) 63-57 56 55 54 FID Use FID Reserved Override Filter VLAN ID, representing one of the 128 active VLANs. 1, use (FID+MAC) to look-up in static table. 0, use MAC only to look-up in static table. Reserved. 1, override spanning tree "transmit enable = 0" or "receive enable = 0* setting. This bit is used for spanning tree implementation. 0, no override. 1, this entry is valid, the look-up result will be used. 0, this entry is not valid. The 5 bits control the forward ports, example: 00001, forward to Port 1 00010, forward to Port 2 ..... 10000, forward to Port 5 00110, forward to Port 2 and Port 3 11111, broadcasting (excluding the ingress port) 48 bit MAC address. RO RO RO RO 0000000 0 N/A 0
53 52-48
Valid Forwarding Ports
RO RO
0 00000
47-0
MAC Address (DA)
RO
0x0
Format of Static MAC Table for Writes (32 entries) 62-56 55 54 FID Use FID Override Filter VLAN ID, representing one of the 128 active VLANs. 1, use (FID+MAC) to look-up in static table. 0, use MAC only to look-up in static table. 1, override spanning tree "transmit enable = 0" or "receive enable = 0" setting. This bit is used for spanning tree implementation. 0, no override. 1, this entry is valid, the look-up result will be used. 0, this entry is not valid. The 5 bits control the forward ports, example: 00001, forward toPort 1 00010, forward to Port 2 ..... 10000, forward to Port 5 00110, forward to Port 2 and Port 3 11111, broadcasting (excluding the ingress port) 48-bit MAC address. Table 15. Static MAC Address Table W W W 0000000 0 0
53 52-48
Valid Forwarding Ports
W W
0 00000
47-0
MAC Address (DA)
W
0x0
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Micrel, Inc. Examples: (1) Static Address Table Read (read the 2 entry) Write to Register 110 with 0x10 (read static table selected) Write to Register 111 with 0x1 (trigger the read operation) Then Read Register 113 (63-56) Read Register 114 (55-48) Read Register 115 (47-40) Read Register 116 (39-32) Read Register 117 (31-24) Read Register 118 (23-16) Read Register 119 (15-8) Read Register 120 (7-0) (2) Static Address Table Write (write the 8 entry) Write to Register 110 with 0x10 (read static table selected) Write Register 113 (62-56) Write Register 114 (55-48) Write Register 115 (47-40) Write Register 116 (39-32) Write Register 117 (31-24) Write Register 118 (23-16) Write Register 119 (15-8) Write Register 120 (7-0) Write to Register 110 with 0x00 (write static table selected) Write to Register 111 with 0x7 (trigger the write operation)
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VLAN Table
The VLAN table is used for VLAN table look-up. If 802.1q VLAN mode is enabled (Register 5 bit 7 = 1), this table is used to retrieve VLAN information that is associated with the ingress packet. The fields includes FID (filter ID), Valid and VLAN membership need initializtion, due to provide 4K spacing for the VLAN table, there is no VID filed bits, VID is used as address index to input up to 4096 entries with bits [12:0] information.
Address Name Description Mode Initial Value suggestion 0 11111
Format of Static VLAN Table (Support Max 4096 VLAN ID entries and 128 Active VLANs) 12 11-7 Valid Membership 1, the entry is valid. 0, entry is invalid. Specify which ports are members of the VLAN. If a DA look-up fails (no match in both static and dynamic tables), the packet associated with this VLAN will be forwarded to ports specified in this field. E.g., 11001 means Ports 5, 4, and 1 are in this VLAN. Filter ID. KSZ8895MQ/RQ/FMQ supports 128 active VLANs represented by these seven bit fields. FID is the mapped ID. If 802.1q VLAN is enabled, the look-up will be based on FID+DA and FID+SA. Table 16. VLAN Table R/W R/W
6-0
FID
R/W
0
If 802.1q VLAN mode is enabled, KSZ8895MQ/RQ/FMQ assigns a VID to every ingress packet. If the packet is untagged or tagged with a null VID, the packet is assigned with the default port VID of the ingress port. If the packet is tagged with non-null VID, the VID in the tag is used. The look-up process starts from the VLAN table look-up based on VID number. If the entry is not valid in VLAN table, the packet is dropped and no address learning occurs. If the entry is valid, then the FID is retrieved. The FID+DA and FID+SA lookups are performed. The FID+DA look-up determines the forwarding ports. If FID+DA fails, the packet is broadcast to all the members (excluding the ingress port) of the VLAN. If FID+SA fails, then the FID+SA is learned. The VLAN table configuration is organized as 1024 VLAN sets, each VLAN set consists of 4 VLAN entries, to support up to 4096 VLAN entries. Each VLAN set has 52 bits and should be read or written at the same time specified by the indirect address. The VLAN entries in the VLAN set is mapped to indirect data registers as follow: Entry0[12:0] maps to the VLAN set bits[12-0] {register119[4:0], register120[7:0]} Entry1[12:0] maps to the VLAN set bits[25-13]{register117[1:0], register118[7:0], register119[7:5]} Entry2[12:0] maps to the VLAN set bits[38-26]{register116[6:0], register117[7:2]} Entry3[12:0] maps to the VLAN set bits[51-39]{register114[3:0], register115[7:0], register116[7]} In order to read one VLAN entry, the VLAN set is read first and the specific VLAN entry information can be extracted. To update any VLAN entry, the VLAN set is read first then only the desired VLAN entry is updated and the whole VLAN set is written back. Due to FID in VLAN table is 7-bit, so the VLAN table supports unique 128 flow VLAN groups. Each VLAN set address is 10 bits long (Maximum is 1024) in the indirect address register 110 and 111, the bit [9-8] of VLAN set address is at bit [1-0] of register 110, and the bit [7-0] of VLAN set address is at bit [7-0] of register 111. Each Write and Read can access to four consecutive VLAN entries. Examples: (1) VLAN Table Read (read the VID=2 entry) Write the indirect control and address registers first Write to Register 110 (0x6E) with 0x14 (read VLAN table selected) Write to Register 111 (0x6F) with 0x0 (trigger the read operation for VID=0, 1, 2, 3 entries) Then read the indirect data registers bits [38-26] for VID=2 entry Read Register 116 (0x74), (register116[6:0] are bits 12-6 of VLAN VID=2 entry) January 2011 91
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Micrel, Inc. Read Register 117 (0x75), (register117[7:2] are bits 5-0 of VLAN VID=2 entry) (2) VLAN Table Write (write the VID=10 entry) Read the VLAN set that contains VID=8, 9, 10, 11. Write to Register 110 (0x6E) with 0x14 (read VLAN table selected)
KSZ8895MQ/RQ/FMQ
Write to Register 111 (0x6F) with 0x02 (trigger the read operation and VID=8, 9, 10, 11 indirect address) Read the VLAN set first by the indirect data registers 114, 115, 116, 117, 118, 119, 120. Modify the indirect data registers bits [38-26] by the register 116 bit [6-0] and register 117 bit [7-2] as follows: Write to Register 116 (0x74), (register116[6:0] are bits 12-6 of VLAN VID=10 entry) Write to Register 117 (0x75), (register117[7:2] are bits 5-0 of VLAN VID=10 entry) Then write the indirect control and address registers Write to Register 110 (0x6E) with 0x04 (write VLAN table selected) Write to Register 111 (0x6F) with 0x02 (trigger the write operation and VID=8, 9, 10, 11 indirect address) The table of the follow shows the relationship of the indirect address/data registers and VLAN ID.
Indirect Address high/low bit[9-0] for VLAN sets 0 0 0 0 1 1 1 1 2 2 2 2 : : : 1023 1023 1023 1023 Indirect Data Registers Bits for each VLAN entry Bits[12-0] Bits[25-13] Bits[38-26] Bits[51-39] Bits[12-0] Bits[25-13] Bits[38-26] Bits[51-39] Bits[12-0] Bits[25-13] Bits[38-26] Bits[51-39] : : : Bits[12-0] Bits[25-13] Bits[38-26] Bits[51-39] VID Numbers 0 1 2 3 4 5 6 7 8 9 10 11 : : : 4092 4093 4094 4095 VID bit[12-2] in VLAN Tag 0 0 0 0 1 1 1 1 2 2 2 2 : : : 1023 1023 1023 1023 VID bit[1-0] in VLAN Tag 0 1 2 3 0 1 2 3 0 1 2 3 : : : 0 1 2 3
Table 17. VLAN ID and Indirect Registers
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Dynamic MAC Address Table
This table is read only. The contents are maintained by the KSZ8895MQ/RQ/FMQ only.
Address Name Description Mode Default Format of Dynamic MAC Address Table (1K entries) 71 70-61 MAC Empty No of Valid Entries 1, there is no valid entry in the table. 0, there are valid entries in the table. Indicates how many valid entries in the table. 0x3ff means 1K entries 0x1 and bit 71 = 0: means 2 entries 0x0 and bit 71 = 0: means 1 entry 0x0 and bit 71 = 1: means 0 entry 2-bit counters for internal aging The source port where FID+MAC is learned. 000 Port 1 001 Port 2 010 Port 3 011 Port 4 100 Port 5 1, The entry is not ready, retry until this bit is set to 0. 0, The entry is ready. Filter ID. 48-bit MAC address. Table 18. Dynamic MAC Address Table RO RO 1 0
60-59 58-56
Time Stamp Source Port
RO RO 0x0
55 54-48 47-0
Data Ready FID MAC Address
RO RO RO 0x0 0x0
Examples: (1) Dynamic MAC Address Table Read (read the 1 entry), and retrieve the MAC table size Write to Register 110 with 0x18 (read dynamic table selected) Write to Register 111 with 0x0 (trigger the read operation) and then Read Register 112 (71-64) Read Register 113 (63-56); // the above two registers show # of entries Read Register 114 (55-48) // if bit 55 is 1, restart (reread) from this register Read Register 115 (47-40) Read Register 116 (39-32) Read Register 117 (31-24) Read Register 118 (23-16) Read Register 119 (15-8) Read Register 120 (7-0) (2) Dynamic MAC Address Table Read (read the 257 entry), without retrieving # of entries information Write to Register 110 with 0x19 (read dynamic table selected) Write to Register 111 with 0x1 (trigger the read operation) and then Read Register 112 (71-64) Read Register 113 (63-56) Read Register 114 (55-48) // if bit 55 is 1, restart (reread) from this register Read Register 115 (47-40) Read Register 116 (39-32) Read Register 117 (31-24) Read Register 118 (23-16) Read Register 119 (15-8) Read Register 120 (7-0)
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MIB (Management Information Base) Counters
The MIB counters are provided on per port basis. These counters are read using indirect memory access as below: For Port 1
Offset 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F Counter Name RxLoPriorityByte RxHiPriorityByte RxUndersizePkt RxFragments RxOversize RxJabbers RxSymbolError RxCRCerror RxAlignmentError RxControl8808Pkts RxPausePkts RxBroadcast RxMulticast RxUnicast Rx64Octets Rx65to127Octets Rx128to255Octets Rx256to511Octets Rx512to1023Octets Rx1024to1522Octets TxLoPriorityByte TxHiPriorityByte TxLateCollision TxPausePkts TxBroadcastPkts TxMulticastPkts TxUnicastPkts TxDeferred TxTotalCollision TxExcessiveCollision TxSingleCollision TxMultipleCollision Description Rx lo-priority (default) octet count including bad packets. Rx hi-priority octet count including bad packets. Rx undersize packets w/good CRC. Rx fragment packets w/bad CRC, symbol errors or alignment errors. Rx oversize packets w/good CRC (max: 1536 or 1522 bytes). Rx packets longer than 1522B w/either CRC errors, alignment errors, or symbol errors (depends on max packet size setting) or Rx packets longer than 1916B only. Rx packets w/ invalid data symbol and legal preamble, packet size. Rx packets within (64,1522) bytes w/an integral number of bytes and a bad CRC (upper limit depends on max packet size setting). Rx packets within (64,1522) bytes w/a non-integral number of bytes and a bad CRC (upper limit depends on max packet size setting). The number of MAC control frames received by a port with 88-08h in EtherType field. The number of PAUSE frames received by a port. PAUSE frame is qualified with EtherType (8808h), DA, control opcode (00-01), data length (64B min), and a valid CRC. Rx good broadcast packets (not including errored broadcast packets or valid multicast packets). Rx good multicast packets (not including MAC control frames, errored multicast packets or valid broadcast packets). Rx good unicast packets. Total Rx packets (bad packets included) that were 64 octets in length. Total Rx packets (bad packets included) that are between 65 and 127 octets in length. Total Rx packets (bad packets included) that are between 128 and 255 octets in length. Total Rx packets (bad packets included) that are between 256 and 511 octets in length. Total Rx packets (bad packets included) that are between 512 and 1023 octets in length. Total Rx packets (bad packets included) that are between 1024 and 1522 octets in length (upper limit depends on max packet size setting). Tx lo-priority good octet count, including PAUSE packets. Tx hi-priority good octet count, including PAUSE packets. The number of times a collision is detected later than 512 bit-times into the Tx of a packet. The number of PAUSE frames transmitted by a port. Tx good broadcast packets (not including errored broadcast or valid multicast packets). Tx good multicast packets (not including errored multicast packets or valid broadcast packets). Tx good unicast packets. Tx packets by a port for which the 1st Tx attempt is delayed due to the busy medium. Tx total collision, half-duplex only. A count of frames for which Tx fails due to excessive collisions. Successfully Tx frames on a port for which Tx is inhibited by exactly one collision. Successfully Tx frames on a port for which Tx is inhibited by more than one collision.
Table 19. Port1 MIB Counter Indirect Memory Offerts
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Micrel, Inc. For port 2, the base is 0x20, same offset definition (0x20-0x3f) For port 3, the base is 0x40, same offset definition (0x40-0x5f) For port 4, the base is 0x60, same offset definition (0x60-0x7f) For port 5, the base is 0x80, same offset definition (0x80-0x9f)
Address 31 30 29-0 Name Overflow Count Valid Counter Values Description 1, Counter overflow. 0, No Counter overflow. 1, Counter value is valid. 0, Counter value is not valid. Counter value. Table 20. Format of "Per Port" MIB Counter
KSZ8895MQ/RQ/FMQ
Mode RO RO RO
Default 0 0 0
Format of Per Port MIB Counters (16 entries)
Offset 0x100 0x101 0x102 0x103 0x104 0x105 0x106 0x107 0x108 0x109
Counter Name Port1 Tx Drop Packets Port2 Tx Drop Packets Port3 Tx Drop Packets Port4 Tx Drop Packets Port5 Tx Drop Packets Port1 Rx Drop Packets Port2 Rx Drop Packets Port3 Rx Drop Packets Port4 Rx Drop Packets Port5 Rx Drop Packets
Description Tx packets dropped due to lack of resources. Tx packets dropped due to lack of resources. Tx packets dropped due to lack of resources. Tx packets dropped due to lack of resources. Tx packets dropped due to lack of resources. Rx packets dropped due to lack of resources. Rx packets dropped due to lack of resources. Rx packets dropped due to lack of resources. Rx packets dropped due to lack of resources. Rx packets dropped due to lack of resources. Table 21. All Port Dropped Packet MIB Counters
Address
Name
Description
Mode
Default
Format of All Port Dropped Packet MIB Counters 30-16 15-0 Reserved Counter Values Reserved. Counter value. Table 22. Format of "All Dropped Packet" MIB Counter
Note: All port dropped packet MIB counters do not indicate overflow or validity; therefore the application must keep track of overflow and valid conditions.
N/A RO
N/A 0
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The KSZ8895MQ/RQ/FMQ provides a total of 34 MIB counter per port. These counter are used to monitor the port detail activity for network management and maintenance. These MIB counters are read using indirect memory access as follows examples. Programming Examples: (1) MIB counter read (read port 1 Rx64Octets counter) Write to Register 110 with 0x1c (read MIB counters selected) Write to Register 111 with 0xe (trigger the read operation) Then Read Register 117 (counter value 31-24) // If bit 31 = 1, there was a counter overflow // If bit 30 = 0, restart (reread) from this register Read Register 118 (counter value 23-16) Read Register 119 (counter value 15-8) Read Register 120 (counter value 7-0) (2) MIB counter read (read port 2 Rx64Octets counter) Write to Register 110 with 0x1c (read MIB counter selected) Write to Register 111 with 0x2e (trigger the read operation) Then Read Register 117 (counter value 31-24) //If bit 31 = 1, there was a counter overflow //If bit 30 = 0, restart (reread) from this register Read Register 118 (counter value 23-16) Read Register 119 (counter value 15-8) Read Register 120 (counter value 7-0) (3) MIB counter read (read port 1 tx drop packets) Write to Register 110 with 0x1d Write to Register 111 with 0x00 Then Read Register 119 (counter value 15-8) Read Register 120 (counter value 7-0)
Note: To read out all the counters, the best performance over the SPI bus is (160+3) x 8 x 80 = 104us, where there are 160 registers, 3 overhead, 8 clocks per access, at 12.5MHz. In the heaviest condition, the byte counter will overflow in 2 minutes. It is recommended that the software read all the counters at least every 30 seconds. The per port MIB counters are designed as "read clear." A per port MIB counter will be cleared after it is accessed. All port dropped packet MIB counters are not cleared after they are accessed. The application needs to keep track of overflow and valid conditions on these counters.
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MIIM Registers
All the registers defined in this section can be also accessed via the SPI interface. Note: different mapping mechanisms used for MIIM and SPI. The "PHYAD" defined in IEEE is assigned as "0x1" for Port 1, "0x2" for Port 2, "0x3" for Port 3, "0x4" for Port 4, and "0x5" for Port 5. The "REGAD" supported are 0x0-0x5 (0h-5h), 0x1D (1dh) and 0x1F (1fh).
Address Name Description Mode Default
Register 0h: MII Control
15 14 Soft Reset Loop Back 1, PHY soft reset. 0, Normal operation. 1 = Perform MAC loopback, loop back path as follows: Assume the loop-back is at Port 1 MAC, Port 2 is the monitor port. Port 1 MAC Loopback (Port 1 reg. 0, bit 14 = `1') Start: RXP2/RXM2 (Port 2). Can also start from port 3, 4, 5 Loopback: MAC/PHY interface of Port 1's MAC End: TXP2/TXM2 (Port 2). Can also end at Ports 3, 4, 5 respectively Setting address ox3,4,5 reg. 0, bit 14 = `1' will perform MAC loopback on Ports 3, 4, 5 respectively. 0 = Normal Operation. 1, 100Mbps. 0, 10Mbps. 1, Auto-negotiation enabled. 0, Auto-negotiation disabled. 1, Power down. 0, Normal operation. 1, Electrical PHY isolation of PHY from Tx+/Tx-. 0, Normal operation. 1, Restart Auto-negotiation. 0, Normal operation. 1, Full duplex. 0, Half duplex. Not supported. 1 = HP Auto MDI/MDI-X mode 0 = Micrel Auto MDI/MDI-X mode 1, Force MDI. 0, Normal operation. 1, Disable auto MDI/MDI-X. 0, Normal operation. 1, Disable far end fault detection. 0, Normal operation. 1, Disable transmit. 0, Normal operation. 1, Disable LED. 0, Normal operation. R/W (SC) R/W 0 0
13 12 11 10 9 8 7 6 5 4 3 2 1 0
Force 100 AN Enable Power Down PHY Isolate Restart AN Force Full Duplex Collision Test Reserved Hp_mdix Force MDI Disable Auto MDI/MDI-X Disable far End fault Disable Transmit Disable LED
R/W R/W R/W R/W R/W R/W RO RO R/W R/W R/W R/W R/W R/W
1 1 0 0 0 0 0 0 1 0 0 0 0 0
Register 1h: MII Status
15 14 13 T4 Capable 100 Full Capable 100 Half Capable 0, Not 100 BASET4 capable. 1, 100BASE-TX full-duplex capable. 0, Not capable of 100BASE-TX full-duplex. 1, 100BASE-TX half-duplex capable. 0, Not 100BASE-TX half-duplex capable. RO RO RO 0 1 1
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Address 12 11 10-7 6 5 4 3 2 1 0 Name 10 Full Capable 10 Half Capable Reserved Preamble Suppressed AN Complete far End fault AN Capable Link Status Jabber Test Extended Capable Not supported. 1, Auto-negotiation complete. 0, Auto-negotiation not completed. 1, far end fault detected. 0, No far end fault detected. 1, Auto-negotiation capable. 0, Not auto-negotiation capable. 1, Link is up. 0, Link is down. Not supported. 0, Not extended register capable. Description 1, 10BASE-T full-duplex capable. 0, Not 10BASE-T full-duplex capable. 1, 10BASE-T half-duplex capable. 0, 10BASE-T half-duplex capable.
KSZ8895MQ/RQ/FMQ
Mode RO RO RO RO RO RO RO RO RO RO Default 1 1 0 0 0 0 1 0 0 0
Register 2h: PHYID HIGH
15-0 Phyid High High order PHYID bits. RO 0x0022
Register 3h: PHYID LOW
15-0 Phyid Low Low order PHYID bits. RO 0x1450
Register 4h: Advertisement Ability
15 14 13 12-11 10 9 8 7 6 5 4-0 Next Page Reserved Remote fault Reserved Pause Reserved Adv 100 Full Adv 100 Half Adv 10 Full Adv 10 Half Selector Field 1, Advertise 100 full-duplex ability. 0, Do not advertise 100 full-duplex ability. 1, Advertise 100 half-duplex ability. 0, Do not advertise 100 half-duplex ability. 1, Advertise 10 full-duplex ability. 0, Do not advertise 10 full-duplex ability. 1, Advertise 10 half-duplex ability. 0, Do not advertise 10 half-duplex ability. 802.3 1, Advertise pause ability. 0, Do not advertise pause ability. Not supported. Not supported. RO RO RO RO R/W R/W R/W R/W R/W R/W RO 0 0 0 0 1 0 1 1 1 1 00001
Register 5h: Link Partner Ability
15 14 13 12-11 10 9 Next Page LP ACK Remote fault Reserved Pause Reserved Link partner pause capability. Not supported. Not supported. Not supported. RO RO RO RO RO RO 0 0 0 0 0 0
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Address 8 7 6 5 4-0 Name Adv 100 Full Adv 100 Half Adv 10 Full Adv 10 Half Reserved Description Link partner 100 full capability. Link partner 100 half capability. Link partner 10 full capability. Link partner 10 half capability.
KSZ8895MQ/RQ/FMQ
Mode RO RO RO RO RO Default 0 0 0 0 00001
Register 1dh: LinkMD Control/Status
15 Vct_enable 1 = Enable cable diagnostic. AfterVCT test has completed, this bit will be self-cleared. 0 = Indicate cable diagnostic test (if enabled) has completed and the status information is valid for read. 00 = Normal condition 01 = Open condition detected in cable 10 = Short condition detected in cable 11 = Cable diagnostic test has failed 1 = Less than 10 meter short Distance to the fault. It's approximately 0.4m*vct_fault_count[8:0] R/W (SC) RO 0
14-13
Vct_result
00
12 11-9 8-0
Vct 10M Short Reserved Vct_fault_count
RO RO RO
0 0 000000000
Register 1fh: PHY Special Control/Status
15-11 10-8 Reserved Port Operation Mode Indication Indicate the current state of port operation mode: [000] = reserved [001] = still in auto-negotiation [010] = 10BASE-T half duplex [011] = 100BASE-TX half duplex [100] = reserved [101] = 10BASE-T full duplex [110] = 100BASE-TX full duplex [111] = PHY/MII isolate
N/A, don't change
RO RO
0000000000 000
7-6
Reserved
R/W
xx
5 4 3 2 1
Polrvs MDI-X status Force_lnk Pwrsave Remote Loopback
1 = Polarity is reversed 0 = Polarity is not reversed 1 = MDI-X 0 = MDI 1 = Force link pass 0 = Normal operation 1 = Enable power save 0 = Disable power save 1 = Perform Remote loopback, loop back path as follows: Port 1 (PHY ID address 0x1 reg. 1f, bit 1 = `1') Start: RXP1/RXM1 (port 1) Loopback: PMD/PMA of port 1's PHY End: TXP1/TXM1 (port 1) Setting PHY ID address 0x2,3,4,5 reg. 1f, bit 1 = `1' will perform remote loopback on port 2, 3, 4, 5. 0 = Normal Operation.
RO RO R/W R/W R/W
0 0 0 0 0
0
Reserved
RO
0
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Absolute Maximum Ratings(1)
Supply Voltage (VDDAR, VDDAP, VDDC) .......................-0.5V to +2.4V (VDDAT, VDDIO) .................................-0.5V to +4.0V Input Voltage ........................................-0.5V to +4.0V Output Voltage .....................................-0.5V to +4.0V Lead Temperature (soldering, 10 sec.) ..............270C Storage Temperature (TS) .................-55C to +150C HBM ESD Rating................................................... 4KV
Operating Ratings(2)
Supply Voltage (VDDAR, VDDAP, VDDC)................... +1.15V to +1.25V (VDDAT) ....................................... +3.15V to +3.45V (VDDIO) ........3.15 to 3.45V or 2.4 to 2.6V or 1.71 to 1.89V Ambient Temperature (TA) Commercial .................................... -0C to +70C Industrial ....................................... -40C to +85C (3) Package Thermal Resistance Thermal Resistance (JA) .....................41.54C/W Thermal Resistance (JC) .....................19.78C/W
Electrical Characteristics(4, 5)
VIN = 1.2V/3.3V (typ.); TA = 25C
Symbol IDX IDda IDDc IDDIO IDX IDda IDDc IDDIO IDX IDda IEDM IDDIO IPSM1 IPSM2 ISPDM1 ISPDM2 IEDM1 IEDM2 VIH VIL IIN VOH Parameter 100BASE-TX (Transmitter) 3.3V Analog 100BASE-TX 1.2V Analog 100BASE-TX 1.2V Digital 100BASE-TX (Digital IO) 3.3V Digital 10BASE-T (Transmitter) 3.3V Analog 10BASE-T 1.2V Analog 10BASE-T 1.2V Digital 10BASE-T (Digital IO) 3.3V Digital 10BASE-T (Transmitter) 3.3V Analog 10BASE-T 1.2V Analog 10BASE-T 1.2V Digital 10BASE-T (Digital IO) 3.3V Digital Power Saving Mode 3.3V Power Saving Mode 1.2V Soft Power Down Mode 3.3V Soft Power Down Mode 1.2V Energy Detect Mode 3.3V Energy Detect Mode 1.2V Input High Voltage Input Low Voltage Input Current (Excluding Pull-up/Pull-down) Output High Voltage VIN = GND ~ VDDIO IOH = -8mA -10 2.4/1.9 /1.5 Condition VDDAT VDDAR VDDC VDDIO VDDAT VDDAR VDDC VDDIO VDDAT VDDAR VDDC VDDIO VDDAT + VDDIO VDDAR + VDDC VDDAT + VDDIO VDDAR + VDDC VDDAT + VDDIO VDDAR + VDDC 2.0/2.0 /1.3 0.8/0. 6/0.3 10 Min Typ 112 40 45 2.5 121 15 56 2 70 39 59 1.5 24 74 1.5 0.28 7.5 46 Max Units mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA V V A V 100BASE-TX Operation--All Ports 100% Utilization
10BASE-T Operation --All Ports 100% Utilization
Auto-Negotiation Mode
Power Management Mode
TTL Inputs
TTL Outputs
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Symbol VOL IOZ Parameter Output Low Voltage Output Tri-State Leakage Condition IOL = 8mA VIN = GND ~ VDDIO 0.95 Min
KSZ8895MQ/RQ/FMQ
Typ Max 0.4/0. 4/0.2 10 1.05 2 3 0 5 0.5 0.5 5 Peak-to-peak 5MHz square wave 0 300 2.2 0.75 400 2.5 1.4 28 1.4 585 2.8 3.5 30 Units V A V % ns ns ns % ns mV V ns ns
100BASE-TX Transmit (measured differentially after 1:1 transformer) 100 termination on the VO Peak Differential Output Voltage differential output 100 termination on the VIMB Output Voltage Imbalance differential output Rise/fall Time tr tt Rise/fall Time Imbalance Duty Cycle Distortion Overshoot Output Jitters 10BASE-T Receive VSQ Squelch Threshold 10BASE-T Transmit (measured differentially after 1:1 transformer) VDDAT = 2.5V 100 termination on the VP Peak Differential Output Voltage differential output Output Jitters Peak-to-peak Rise/fall Times
Notes: 1. Exceeding the absolute maximum rating may damage the device. 2. The device is not guaranteed to function outside its operating rating. Unused inputs must always be tied to an appropriate logic voltage level (ground or VDD). 3. No heat spreader in package. The thermal junction to ambient (JA) and the thermal junction to case (JC) are under air velocity 0m/s. 4. Specification for packaged product only. There is no an additional transformer consumption due to use on chip termination technology with internal biasing for 10Bese-T and 100Base-TX. 5. Measurements were taken with operating ratings.
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Timing Diagrams
EEPROM Timing
ts1 Receive Timin g
tcyc1
th1
SCL SDA
Figure 13. EEPROM Interface Input Receive Timing Diagram
tcyc1 Transmit Timing
SCL SDA
tov1
Figure 14. EEPROM Interface Output Transmit Timing Diagram
Symbol
Parameter
Min
Typ
Max
Units
tCYC1 tS1 tH1 tOV1
Clock Cycle Set-Up Time Hold Time Output Valid
Table 23. EEPROM Timing Parameters
16384 20 20 4096 4112 4128
ns ns ns ns
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Micrel, Inc. SNI Timing
KSZ8895MQ/RQ/FMQ
Receive Timing
ts2
tcyc2
th2
MTXC MTXEN MTXD[0]
Figure 15. SNI Input Timing
tcyc2 Transmit Timing
MRXC MRXDV MCOL MRXD[0]
tov2
Figure 16. SNI Output Timing
Symbol
Parameter
Min
Typ
Max
Units
tCYC2 tS2 tH2 tO2
Clock Cycle Set-Up Time Hold Time Output Valid
Table 24. SNI Timing Parameters
100 10 0 0 3 6
ns ns ns ns
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Micrel, Inc. MII Timing
KSZ8895MQ/RQ/FMQ
Figure 17. MAC Mode MII Timing - Data Received from MII
Figure 18. MAC Mode MII Timing - Data Transmitted from MII
10Base-T/100Base-TX Symbol Parameter Min Typ Max Units
tCYC3 tS3 tH3 tOV3
Clock Cycle Set-Up Time Hold Time Output Valid 10 5 3
400/40
ns ns ns
9
25
ns
Table 25. MAC Mode MII Timing Parameters
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Figure 19. PHY Mode MII Timing - Data Received from MII
Figure 20. PHY Mode MII Timing - Data Transmitted from MII
10BaseT/100BaseT Symbol Parameter Min Typ Max Unit s ns
tCYC4 tS4 tH4 tOV4
Clock Cycle Set-Up Time Hold Time Output Valid 10 0 10
400/40
ns ns 20 25 ns
Table 26. PHY Mode MII Timing Parameters
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Micrel, Inc. RMII Timing
T ran s m it T im in g tcy c
KSZ8895MQ/RQ/FMQ
REFCLK t1 t2 TX_EN T X D [1 :0 ]
Figure 21. RMII Timing - Data Received from RMII
Receive Tim ing
tcyc
REFCLK
CRSDV RXD[1:0]
tod
Figure 22. RMII Timing - Data Transmitted to RMII
Timing Parameter tcyc t1 t2 tod
Description Clock cycle Setup time Hold time Output delay
Min 4 2 3
Typ 20
Max
Unit ns ns ns
14
ns
Table 27. RMII Timing Parameters
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Micrel, Inc. SPI Timing
tSHSL
KSZ8895MQ/RQ/FMQ
SPIS_N tCHSL SPIC tDVCH tCHDX SPID MSB tDLDH tDHDL SPIQ High Impedance tCLCH LSB tSLCH tCHSH
tSHCH
tCHCL
Figure 23. SPI Input Timing
Symbol
Parameter
Min
Typ
Max
Units
fC tCHSL tSLCH tCHSH tSHCH tSHSL tDVCH tCHDX tCLCH tCHCL tDLDH tDHDL
Clock Frequency SPIS_N Inactive Hold Time SPIS_N Active Set-Up Time SPIS_N Active Hold Time SPIS_N Inactive Set-Up Time SPIS_N Deselect Time Data Input Set-Up Time Data Input Hold Time Clock Rise Time Clock fall Time Data Input Rise Time Data Input fall Time
Table 28. SPI Input Timing Parameters
25 10 10 10 10 200 5 5 1 1 1 1
MHz ns ns ns ns ns ns ns s s s s
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KSZ8895MQ/RQ/FMQ
SPIS_N tCH SPIC tCLQV tCLQX SPIQ tQLQH tQHQL SPID LSB tCL tSHQZ
Figure 24. SPI Output Timing
Symbol
Parameter
Min
Typ
Max
Units
fC tCLQX tCLQV tCH tCL tQLQH tQHQL tSHQZ
Clock Frequency SPIQ Hold Time Clock Low to SPIQ Valid Clock High Time Clock Low Time SPIQ Rise Time SPIQ fall Time SPIQ Disable Time
Table 29. SPI Output Timing Parameters
25 0 18 18 50 50 15 0 15
MHz ns ns ns ns ns ns ns
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Micrel, Inc. Auto-Negotiation Timing
KSZ8895MQ/RQ/FMQ
Figure 25: Auto-Negotiation Timing
Symbols
Parameters
Min
Typ
Max
Units
tBTB tFLPW tPW tCTD tCTC
FLP burst to FLP burst FLP burst width Clock/Data pulse width Clock pulse to Data pulse Clock pulse to Clock pulse Number of Clock/Data pulse per burst
8
16 2 100
24
ms ms ns
55.5 111 17
64 128
69.5 139 33
s s
Table 30. Auto-Negotiation Timing Parameters
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Micrel, Inc. MDC/MDIO Timing
KSZ8895MQ/RQ/FMQ
Figure 26. MDC/MDIO Timing
Timing Parameter
Description
Min
Typ
Max
Unit
tP t1MD1 tMD2 tMD3
MDC period MDIO (PHY input) setup to rising edge of MDC MDIO (PHY input) hold from rising edge of MDC MDIO (PHY output) delay from rising edge of MDC
Table 31. MDC/MDIO Typical Timing Parameters
400 10 4 222
ns ns ns ns
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Micrel, Inc. Reset Timing
KSZ8895MQ/RQ/FMQ
Figure 27. Reset Timing
Symbol
Parameter
Min
Typ
Max
Units
tSR tCS tCH tRC
Stable Supply Voltages to Reset High Configuration Set-Up Time Configuration Hold Time Reset to Strap-In Pin Output
10 50 50 50
ms ns ns ns us
tvr
3.3V rise time
Table 32. Reset Timing Parameters
100
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Reset Circuit Diagram Micrel recommends the following discrete reset circuit as shown in Figure 22 when powering up the KS8895MQ device. For the application where the reset circuit signal comes from another device (e.g., CPU, FPGA, etc), we recommend the reset circuit as shown in Figure 23.
Figure 28. Recommended Reset Circuit
Figure 29. Recommended Circuit for Interfacing with CPU/FPGA Reset
At power-on-reset, R, C, and D1 provide the necessary ramp rise time to reset the Micrel device. The reset out RST_OUT_n from CPU/FPGA provides the warm reset after power up.
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Selection of Isolation Transformer(1)
One simple 1:1 isolation transformer is needed at the line interface. An isolation transformer with integrated commonmode choke is recommended for exceeding FCC requirements at line side. Request to separate the center taps of RX/TX at chip side. The following table gives recommended transformer characteristics.
Characteristics Name Value Test Condition
Turns Ratio Open-Circuit Inductance (min.) Leakage Inductance (max.) Inter-Winding Capacitance (max.) D.C. Resistance (max.) Insertion Loss (max.) HIPOT (min.)
1 CT : 1 CT 350H 0.4H 12pF 0.9 1.0dB 1500Vrms
Table 33. Transformer Selection Criteria
100mV, 100kHz, 8mA 1MHz (min.)
0MHz to 65MHz
Note: 1. 2.
The IEEE 802.3u standard for 100BASE-TX assumes a transformer loss of 0.5dB. For the transmit line transformer, insertion loss of up to 1.3dB can be compensated by increasing the line drive current by means of reducing the ISET resistor value. The center taps of RX and TX should be isolated for the low power consumption.
The following transformer vendors provide compatible magnetic parts for Micrel's device:
Vendors and Parts Auto MDIX Number of Ports Vendors and Parts Auto MDIX Number of Ports
Pulse YCL TDK LanKom Datatronic
H1664NL PH406082 TLA-6T718A LF-H41S NT79075
Yes Yes Yes Yes Yes
4 4 1 1 1
Pulse Bel Fuse YCL Transpower Delta
H1102 S558-5999-U7 PT163020 HB726 LF8505
Yes Yes Yes Yes Yes
1 1 1 1 1
Table 34. Qualified Magnetic Vendors
Selection of Reference Crystal
Chacteristics Value Units
Frequency Frequency tolerance (max) Load capacitance (max) Series resistance (max ESR)
25.00000 <= 50 27 40
MHz ppm pF
Table 35. Typical Reference Crystal Characteristics
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Package Information
128-Pin PQFP
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KSZ8895MQ/RQ/FMQ
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry, specifications and descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Micrel's terms and conditions of sale for such products, Micrel assumes no liability whatsoever, and Micrel disclaims any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2010 Micrel, Incorporated.
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